Metal interconnect structures and semi-damascene method for forming the same

Abstract

A first integrated line-and-via structure includes a first via portion embedded within at least one via-level dielectric layer and a first line portion embedded within a lower portion of a dielectric matrix that contacts a top surface of the at least one via-level dielectric layer within a first horizontal plane. The first integrated line-and-via structure includes a first metallic barrier liner and a first main metal portion including a planar portion having sidewalls in direct contact with first surface segments of the dielectric matrix. A second integrated line-and-via structure includes a second via portion contacting the first line portion and further includes a second line portion adjoined to a top end of the second via portion.

What is claimed is: 
     
         1 . A device structure, comprising:
 a first integrated line-and-via structure comprising a first via portion embedded within at least one via-level dielectric layer and a first line portion embedded within a lower portion of a dielectric matrix that contacts a top surface of the at least one via-level dielectric layer within a first horizontal plane, wherein the first integrated line-and-via structure comprises a first metallic barrier liner containing a vertically-extending portion that contacts a sidewall of the at least one via-level dielectric layer and a horizontally-extending portion that contacts a segment of a top surface of the at least one via-level dielectric layer, and further comprises a first main metal portion including a planar portion that overlies the horizontally-extending portion of the first metallic barrier liner and has sidewalls in direct contact with first surface segments of the dielectric matrix; and   a second integrated line-and-via structure comprising a second via portion contacting a first segment of a top surface of the first line portion of the first integrated line-and-via structure within a second horizontal plane and further comprising a second line portion adjoined to a top end of the second via portion.   
     
     
         2 . The device structure of  claim 1 , wherein the second line portion has a top surface within a third horizontal plane at which a top surface of the dielectric matrix is located. 
     
     
         3 . The device structure of  claim 1 , wherein:
 a pair of edges of the first segment of the top surface of the first line portion of the first integrated line-and-via structure coincides with a pair of edges of a bottom surface of the second via portion of the second integrated line-and-via structure;   a pair of sidewalls of the first line portion of the first integrated line-and-via structure is vertically coincident with a pair of sidewalls of the second via portion of the second integrated line-and-via structure; and   a vertical extent of an interface between the one of the sidewalls of the first main metal portion and the dielectric matrix equals a height of the first line portion less a thickness of the horizontally-extending portion of the first metallic barrier liner.   
     
     
         4 . The device structure of  claim 1 , wherein the first main metal portion further comprises a vertically-extending portion that is located in the first via portion and protrudes downward from a bottom surface of the planar portion of the first main metal portion and is laterally surrounded by the vertically-extending portion of the first metallic barrier liner. 
     
     
         5 . The device structure of  claim 1 , further comprising metal lines that are parallel to each other and embedded within a line-level dielectric layer that underlies the via-level dielectric layer, wherein a bottom surface of the first via portion contacts a top surface of one of the metal lines. 
     
     
         6 . The device structure of  claim 1 , wherein:
 the metal lines comprise copper bit lines of a memory device and copper bit-line-level interconnect metal lines that provide an electrical connection between word lines of the memory device and a word line driver circuit;   the first metallic barrier liner comprises tungsten nitride;   the first main metal portion comprises tungsten; and   the second integrated line-and-via structure comprises a copper second main metal portion and a second metallic barrier liner.   
     
     
         7 . The device structure of  claim 1 , further comprising a dielectric hardmask rail that contacts a second segment of the top surface of the first line portion of the first integrated line-and-via structure and having a pair of sidewalls contacting the dielectric matrix. 
     
     
         8 . The device structure of  claim 7 , wherein:
 the dielectric hardmask rail has a top surface within a fourth horizontal plane that contains a horizontal bottom surface of the second line portion of the second integrated line-and-via structure;   a pair of edges of the second segment of the top surface of the first line portion of the first integrated line-and-via structure coincides with a pair of edges of a bottom surface of the dielectric hardmask rail; and   a pair of sidewalls of the first line portion of the first integrated line-and-via structure is vertically coincident with a pair of sidewalls of the dielectric hardmask rail.   
     
     
         9 . The device structure of  claim 7 , wherein the top surface of the first line portion of the first integrated line-and-via structure contacts the dielectric hardmask rail and a bottom surface of the second via portion. 
     
     
         10 . The device structure of  claim 1 , wherein the device structure further comprises:
 a plurality of first integrated line-and-via structures that includes the first integrated line-and-via structure and additional first integrated line-and-via structures, wherein the plurality of first integrated line-and-via structures are laterally spaced apart from each other; and   a plurality of dielectric hardmask rails that includes the dielectric hardmask rail and additional dielectric hardmask rails, wherein each dielectric hardmask rail of the plurality of dielectric hardmask rails has a same width as a respective first line portion of a respective underlying one of the plurality of first integrated line-and-via structures.   
     
     
         11 . The device structure of  claim 10 , further comprising an air gaps embedded within the dielectric matrix and between a respective neighboring pair of the plurality of first integrated line-and-via structures, wherein each of the air gaps comprises a respective bottommost surface located between the first horizontal plane and the second horizontal plane, and a respective topmost surface located between the second horizontal plane and a fourth horizontal plane including top surfaces of the plurality of dielectric hardmask rails. 
     
     
         12 . A three-dimensional memory device, comprising:
 an alternating stack of insulating layers and word lines;   memory opening fill structures extending through the alternating stack and each comprising a memory film, a vertical semiconductor channel, and a drain region;   copper bit lines electrically connected to the drain regions;   copper bit-line-level interconnect metal lines located at a same level as the copper bit lines and electrically connected to the word lines;   first integrated line-and-via structures contacting the respective copper bit lines and copper bit-line-level interconnect metal lines, and comprising a tungsten nitride metallic barrier liner and a tungsten first main metal portion; and   second integrated line-and-via structures contacting the respective first integrated line-and-via structures and comprising a second metallic barrier liner and a copper second main metal portion.   
     
     
         13 . The three-dimensional memory device of  claim 12 , further comprising a dielectric matrix located in contact with sidewalls of the tungsten first main metal portion. 
     
     
         14 . The three-dimensional memory device of  claim 13 , further comprising air gaps located in the dielectric matrix between the first integrated line-and-via structures. 
     
     
         15 . The three-dimensional memory device of  claim 13 , further comprising silicon nitride rails that contact a top surface of the first integrated line-and-via structures and having a pair of sidewalls contacting the dielectric matrix. 
     
     
         16 . A method of forming device structure, comprising:
 forming a first via cavity through at least one via-level dielectric layer;   depositing and patterning a first metallic barrier material, a first main metal, and a dielectric hardmask material over the at least one via-level dielectric layer, wherein a patterned portion of the first metallic barrier material and the first main metal comprises a first integrated line-and-via structure that includes a first via portion embedded within the at least one via-level dielectric layer and a first line portion overlying a first horizontal plane including a top surface of the at least one via-level dielectric layer, and a patterned portion of the dielectric hardmask material comprises a dielectric hardmask rail that overlies the first line portion;   forming a dielectric matrix over the dielectric hardmask rail and the at least one via-level dielectric layer;   forming a line cavity in an upper portion of the dielectric matrix such that a first portion of the dielectric hardmask rail is exposed while a second portion of the dielectric hardmask rail is not exposed;   forming a second via cavity by removing the first portion of the dielectric hardmask rail without removing the second portion of the dielectric hardmask rail; and   forming a second integrated line-and-via structure in a combined volume of the line cavity and the second via cavity.   
     
     
         17 . The method of  claim 16 , further comprising:
 forming a patterned etch mask layer over the dielectric hardmask material; and   performing an anisotropic etch process that etches unmasked portions of the dielectric hardmask material, the first main metal, and the first metallic barrier material from above the first horizontal plane employing the patterned etch mask layer as an etch mask, wherein:   a combination of remaining portions of the first main metal and the first metallic barrier material comprises the first integrated line-and-via structure; and   a remaining portion of the dielectric hardmask material comprises the dielectric hardmask rail.   
     
     
         18 . The method of  claim 16 , wherein the second via cavity is formed by performing a selective anisotropic etch process that etches a material of the dielectric hardmask rail selective to materials of the dielectric matrix and the first main metal. 
     
     
         19 . The method of  claim 16 , wherein:
 additional patterned portions of the first metallic barrier material and the first main metal comprise additional first integrated line-and-via structures;   additional patterned portions of the dielectric hardmask material comprise additional dielectric hardmask rails; and   the dielectric matrix is deposited around the first integrated line-and-via structure, the additional first integrated line-and-via structures, the dielectric hardmask rail, and the additional dielectric hardmask rails.   
     
     
         20 . The method of  claim 16 , wherein:
 the first integrated line-and-via structure is formed by a semi-damascene process;   the first metallic barrier material comprises tungsten nitride and the first main metal comprises tungsten; and   second integrated line-and-via structure comprising a second metallic barrier liner and a copper second main metal portion is formed by a dual damascene process in contact with the first integrated line-and-via structure.