Techniques for improving host write performance during data folding
Abstract
Methods, systems, and devices for techniques for improving host write performance during data transferring (e.g., folding) are described. A memory system may determine to transfer first data from one or more source data blocks of the memory system to one or more destination data blocks, where the source data blocks and the destination data blocks are associated with one or more memory dies of a set of memory dies of the memory system. The memory system may also receive, from a host system, a command to write second data to a first memory die of the one or more memory dies, and write, concurrent with transferring the first data, the second data to a second memory die of the set of memory dies different than the one or more memory dies based on the transfer of the first data being associated with the first memory die.
Claims
exact text as granted — not AI-modified1 . (canceled)
2 . A memory system, comprising:
one or more memory dies; and one or more controllers coupled with the one or more memory dies and configured to cause the memory system to:
receive a command to write first data to a first memory die of the one or more memory dies;
write the first data to a second memory die of the one or more memory dies concurrent with a transfer of second data from one or more source data blocks of the memory system to one or more destination data blocks of the memory system; and
perform, after transferring the second data and after writing the first data, a fold operation on the first data, wherein the first data is reordered from a first order associated with writing the first data to a second order of a sequential read of the first data in accordance with the fold operation.
3 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
perform, according to the second order, the sequential read of the first data from respective pages of one or more pages of a same pageline in accordance with the first data being transferred to the one or more pages of the same pageline of the one or more memory dies via the fold operation.
4 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
read, after transferring the second data and after writing the first data, the first data from one or more pages of a pageline included in the second memory die; generate first parity data associated with the first data in accordance with reading the first data; and store the first parity data to one or more retention data blocks of the memory system.
5 . The memory system of claim 4 , wherein the one or more controllers are further configured to cause the memory system to:
write, after transferring the second data, third data to one or more remaining pages of the pageline in accordance with receiving one or more additional commands, the one or more remaining pages included in the one or more memory dies; generate second parity data associated with the third data in accordance with writing the third data to the one or more remaining pages of the pageline; and generate third parity data associated with the pageline in accordance with the first parity data and the second parity data in accordance with storing the first parity data, wherein the third parity data comprises redundant array of independent not-and (NAND) parity data.
6 . The memory system of claim 5 , wherein the one or more controllers are further configured to cause the memory system to:
perform a first exclusive-or (XOR) operation on the first data of each page of the one or more pages of the pageline, wherein the first parity data is in accordance with the first XOR operation; perform a second XOR operation on the third data of each page of the one or more remaining pages of the pageline, wherein the second parity data is in accordance with the second XOR operation; and perform a third XOR operation on the first parity data and the second parity data, wherein the third parity data is in accordance with the third XOR operation;
7 . The memory system of claim 5 , wherein the one or more controllers are further configured to cause the memory system to:
receive an indication of a power-off of the memory system; store the first parity data to the second memory die in accordance with the indication; and read, after a power-on of the memory system, the first parity data, wherein generating the third parity data is in accordance with the reading the first parity data.
8 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
receive a third command to write third data to the first memory die; and write the third data to the first memory die of the one or more memory dies in accordance with a completion of the transfer of the second data.
9 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
receive an indication of a power-off of the memory system; store, before the power-off of the memory system, an indication of a respective last-written-to page of each memory die of the one or more memory dies; read, in accordance with a power-on of the memory system, the indication to determine the respective last-written-to page of each memory die; and write third data to a next page after a last-written-to page of one of the one or more memory dies in accordance with the reading.
10 . The memory system of claim 2 , wherein:
the one or more source data blocks comprise single-level cells, multi-level cells, tri-level cells, or any combination thereof, and the one or more destination data blocks comprise quad-level cells.
11 . A memory system, comprising:
one or more memory dies; and one or more controllers coupled with the one or more memory dies and configured to cause the memory system to:
receive a command to write first data to a first memory die of the one or more memory dies;
transfer, in accordance with a fold operation, second data from one or more source data blocks in one or more first memory dies of the memory system to one or more destination data blocks in the one or more first memory dies, the one or more first memory dies comprising the first memory die; and
write, concurrent with transferring the second data, the first data to a second memory die of the memory system that is different than the one or more first memory dies associated with the transfer of the first data.
12 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
store the first data in a buffer of the memory system, wherein writing the first data to the second memory die is in accordance with storing the first data in the buffer.
13 . The memory system of claim 12 , wherein the one or more controllers are further configured to cause the memory system to:
allocate a portion of a volatile memory system of the memory system as the buffer, wherein a size of the allocated portion is in accordance with a quantity of planes included in each die of the one or more memory dies, a quantity of pages included in each plane of the quantity of planes, and a storage cell type of each page of the quantity of pages.
14 . The memory system of claim 12 , wherein the one or more controllers are further configured to cause the memory system to:
allocate a first portion of the buffer for storage of data to be written to the one or more first memory dies associated with the transfer of the first data, wherein a size of the first portion of the buffer is in accordance with a write mode of the memory system, a storage cell type associated with the write mode of the memory system, or both; and allocate a second portion of the buffer for data associated with one or more third dies of the one or more memory dies of the memory system different from the one or more first memory dies associated with the transfer of the first data.
15 . The memory system of claim 12 , wherein the one or more controllers are further configured to cause the memory system to:
receive, from a host system, a command to write third data to the first memory die and a command to write fourth data to the second memory die; store the third data and the fourth data in the buffer; write, from the buffer and concurrent with transferring the second data, the first data to a third memory die of the one or more memory dies of the memory system that is different than the one or more first memory dies associated with the transfer of the first data; and write, from the buffer and concurrent with transferring the second data, the fourth data to the second memory die in accordance with the second memory die being different than the one or more first memory dies associated with the transfer of the first data.
16 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
allocate a portion of a volatile memory system of the memory system for receiving one or more commands comprising the command to write the first data, wherein writing the first data to the second memory die of the one or more memory dies is in accordance with the allocation of the portion of the volatile memory system for receiving the one or more commands.
17 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
transfer, in accordance with the fold operation and after transferring the second data, the first data from one or more second source data blocks associated with the second memory die to one or more second destination data blocks of the memory system.
18 . The memory system of claim 11 , wherein writing the first data is configured to cause the memory system to:
write the first data to the second memory die concurrent with transferring the second data in accordance with a quantity of available source data blocks of the memory system failing to satisfy a threshold quantity.
19 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
receive a third command to write third data to the first memory die; and write the third data to the first memory die of the one or more memory dies in accordance with a completion of the transfer of the second data.
20 . The memory system of claim 11 , wherein the one or more source data blocks comprise low-density cells including single-level cells, multi-level cells, tri-level cells, or any combination thereof, and the one or more destination data blocks comprise high-density cells including quad-level cells, and wherein the one or more controllers are further configured to cause the memory system to:
transfer, in accordance with the fold operation, the second data from low-density cells of the one or more source data blocks to the high-density cells of the one or more destination data blocks.
21 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
receive a command to write first data to a first memory die of one or more memory dies of a memory system; and write the first data to a second memory die of the one or more memory dies concurrent with a transfer of second data from one or more source data blocks of the memory system to one or more destination data blocks of the memory system; and perform, after transferring the second data and after writing the first data, a fold operation on the first data, wherein the first data is reordered from a first order associated with writing the first data to a second order of a sequential read of the first data in accordance with the fold operation.Join the waitlist — get patent alerts
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