Controlled Transition Between Configuration Mode and User to Reduce Current-Resistance Voltage Drop

Abstract

Systems or methods of the present disclosure may provide for gradually adjusting a frequency of a clock signal. When transitioning from a configuration mode to a user mode, a clock of an integrated circuit (e.g., a field-programmable gate array or FPGA) may quickly (e.g., instantaneously) switch from a low configuration mode frequency to a high user mode frequency. This rapid increase in clock frequency may cause an inrush current and corresponding current-resistance voltage (IR) drop. To reduce or avoid the inrush current and IR drop, a frequency of the clock may be gradually ramped up from the configuration mode frequency to the user mode frequency.

What is claimed is: 
     
         1 . An integrated circuit system comprising:
 programmable logic circuitry to be configured with a user system design during a configuration mode using a clock signal having a first frequency, wherein the programmable logic circuitry comprises a plurality of sectors with different clocks having a plurality of frequencies;   clock circuitry that generates the clock signal; and   control circuitry that directs the clock circuitry to change from the first frequency to the plurality of frequencies over a period of time when transitioning from the configuration mode.   
     
     
         2 . The integrated circuit system of  claim 1 , wherein the control circuitry directs the clock circuitry to ramp from the first frequency to the plurality of frequencies over the period of time. 
     
     
         3 . The integrated circuit system of  claim 2 , wherein the control circuitry directs the clock circuitry to ramp linearly from the first frequency to at least one of the plurality of frequencies over the period of time. 
     
     
         4 . The integrated circuit system of  claim 2 , wherein a second frequency of the plurality of frequencies is used in a first sector of the plurality of sectors, a third frequency of the plurality of frequencies is used in a second sector of the plurality of sectors. 
     
     
         5 . The integrated circuit system of  claim 4 , wherein the ramp from the first frequency to the second frequency are implemented using different ramping techniques. 
     
     
         6 . The integrated circuit system of  claim 5 , wherein the ramp from the first frequency to the second frequency is linear, and the ramp from the first frequency to the third frequency is nonlinear. 
     
     
         7 . The integrated circuit system of  claim 5 , wherein the ramp from the first frequency to the second frequency is continuous, and the ramp from the first frequency to the third frequency is a stepwise function. 
     
     
         8 . The integrated circuit system of  claim 1 , wherein the control circuitry comprises one or more phase-locked loops to change from the first frequency to the plurality of frequencies by gradually increasing feedback divider values of the one or more phase-locked loops. 
     
     
         9 . The integrated circuit system of  claim 1 , wherein the control circuitry comprises a state machine. 
     
     
         10 . The integrated circuit system of  claim 1 , wherein the control circuitry comprises a processor executing instructions. 
     
     
         11 . The integrated circuit system of  claim 1 , wherein the control circuitry and the programmable logic circuitry are disposed on a same circuit. 
     
     
         12 . The integrated circuit system of  claim 1 , wherein the clock circuitry is external to the programmable logic circuitry. 
     
     
         13 . A method, comprising:
 configuring programmable logic circuitry of an integrated circuit in a configuration mode using a clock at a first frequency, wherein the programmable logic circuitry comprises a plurality of sectors with different clocks having a plurality of frequencies;   increasing the clock from the first frequency to a second frequency of the plurality of frequencies over a first period for a first sector of the plurality of sectors utilizing the second frequency;   increasing the clock from the first frequency to a third frequency of the plurality of frequencies over a second period for a second sector of the plurality of sectors utilizing the third frequency;   operating the first sector of the programmable logic circuitry using the second frequency; and   operating the second sector of the programmable logic circuitry using the third frequency.   
     
     
         14 . The method of  claim 13 , wherein increasing the clock from the first frequency to the second frequency over the first period comprises a linear change of clock frequency for the first sector, and increasing the clock from the first frequency to the third frequency over the second period comprises a nonlinear change of clock frequency for the second sector. 
     
     
         15 . The method of  claim 13 , wherein increasing the clock from the first frequency to the second frequency over the first period comprises a continuous change of clock frequency for the first sector, and increasing the clock from the first frequency to the third frequency over the second period comprises a stepwise change of clock frequency for the second sector. 
     
     
         16 . The method of  claim 13 , comprising:
 increasing the clock from the first frequency to a fourth frequency of the plurality of frequencies over a third period for a third sector of the plurality of sectors utilizing the fourth frequency; and   operating the third sector of the programmable logic circuitry using the fourth frequency.   
     
     
         17 . The method of  claim 13 , comprising supplying power to the integrated circuit using a lower guardband that is based at least in part on a ramp function from the first frequency to the second frequency or from the first frequency to the third frequency. 
     
     
         18 . A tangible, non-transitory, computer-readable medium, comprising computer-readable instructions that, when executed by one or more processors of an electronic device, cause the electronic device to:
 receive a system design for an integrated circuit; and   direct the integrated circuit to:
 configure programmable logic circuitry of the integrated circuit having a plurality of sectors with the system design in a configuration mode at a first frequency, wherein configuring the programmable logic circuitry comprises the plurality of sectors to be used with a plurality of frequency clocks; 
 ramp the first frequency to a second frequency of the plurality of frequency clocks over a first period of time; 
 ramp the first frequency to a third frequency of the plurality of frequency clocks over a second period of time; and 
 operate the system design in a first sector of the plurality of sectors using the second frequency and in a second sector of the plurality of sectors using the third frequency. 
   
     
     
         19 . The tangible, non-transitory, computer-readable medium of  claim 18 , wherein ramping the first frequency to the second frequency over the first period comprises a linear change of the clock frequency for the first sector, and ramping the first frequency to the third frequency over the second period comprises a nonlinear change of the clock frequency for the second sector. 
     
     
         20 . The tangible, non-transitory, computer-readable medium of  claim 18 , wherein ramping the first frequency to the second frequency over the first period comprises a continuous change of the clock frequency for the first sector, and ramping the first frequency to the third frequency over the second period comprises a stepwise change of the clock frequency for the second sector.