Low dropout regulator, semiconductor device including same and method of controlling same

Abstract

A low-dropout (LDO) regulator includes a plurality of power transistors connected in parallel between an input node to which an input voltage is applied and an output node, a comparator that compares an output voltage of the output node with a reference voltage and outputs a control signal, a controller that outputs a control code that controls at least some of the plurality of transistors based on the control signal such that an output current equal to an aim current flows through the output node, and a current limit circuit that detects a target current output from a sample transistor connected to the input node and outputs a target code corresponding to the target current. The controller determines a limit code based on the target code and a preset maximum current, and outputs the control code within a range defined by the limit code.

What is claimed is: 
     
         1 . A low-dropout (LDO) regulator, comprising:
 a plurality of power transistors connected in parallel between an input node to which an input voltage is applied and an output node;   a comparator configured to compare an output voltage of the output node with a reference voltage, and output a control signal based on a comparison result obtained by comparing the output voltage with the reference voltage;   a controller configured to output a control code that controls at least some of the plurality of power transistors based on the control signal such that an output current equal to an aim current flows through the output node; and   a current limit circuit configured to detect a target current output from a sample transistor connected to the input node and output a target code corresponding to the target current,   wherein the controller is configured to determine a limit code based on the target code and a preset maximum current, and output the control code within a range defined by the limit code.   
     
     
         2 . The LDO regulator of  claim 1 , wherein the current limit circuit includes:
 a sensing circuit configured to detect the target current;   a converting circuit configured to convert the target current into a target voltage corresponding to the target current; and   an analog-to-digital converter (ADC) configured to convert the target voltage into the target code.   
     
     
         3 . The LDO regulator of  claim 2 , wherein the sensing circuit includes a first transistor connected between the sample transistor and a ground, and an error amplifier connected to the first transistor,
 a first input terminal of the error amplifier is connected to the output node,   a second input terminal of the error amplifier is connected to a first node between the sample transistor and the first transistor,   an output terminal of the error amplifier is connected to a gate electrode of the first transistor, and   the output voltage is applied to the first node.   
     
     
         4 . The LDO regulator of  claim 3 , wherein the converting circuit includes:
 a first resistor and a second transistor connected in series between the input node and the ground;   a first capacitor connected between a second node between the first resistor and the second transistor, and the input node;   a second capacitor connected between a third node between the first capacitor and the input node, and the ground;   a first switch connected between the input node and the third node;   a second switch connected between the first capacitor and the second node;   a third switch connected between the first capacitor and the ground; and   a fourth switch connected between the third node and the second capacitor.   
     
     
         5 . The LDO regulator of  claim 4 , wherein the first switch and the second switch are turned on and off repeatedly according to a specified cycle, and
 the third switch and the fourth switch are turned off while the first switch and the second switch are turned on, and are turned on while the first switch and the second switch are turned off.   
     
     
         6 . The LDO regulator of  claim 5 , wherein the ADC is further configured to convert the target voltage into the target code and output the target code in response to the target voltage being stored at two terminals of the second capacitor. 
     
     
         7 . The LDO regulator of  claim 1 , wherein the controller is further configured to:
 identify the target current based on the target code;   calculate a maximum number of transistors to be turned on among the plurality of power transistors based on the target current and the preset maximum current; and   output the control code within the range defined by the limit code corresponding to the maximum number, and turn on a number of transistors, among the plurality of transistors, less than or equal to the maximum number, in response to the outputted control code.   
     
     
         8 . The LDO regulator of  claim 7 , wherein the controller is further configured to:
 decrease the control code by a unit code in response to a decrease signal output from the comparator when the output voltage is greater than the reference voltage; and   increase the control code by the unit code within the range defined by the limit code in response to an increase signal output from the comparator when the output voltage is less than the reference voltage.   
     
     
         9 . The LDO regulator of  claim 3 , further comprising:
 an output capacitor connected between the output node and the ground,   wherein a charge stored in the output capacitor moves to the output node when the output voltage is less than the reference voltage.   
     
     
         10 . The LDO regulator of  claim 1 , wherein each of the plurality of power transistors has a size equal to a first integer multiple of the sample transistor, and
 a current equal to the first integer multiple of the target current flows from the input node to the output node through each of the plurality of power transistors.   
     
     
         11 . A method of controlling a low-dropout (LDO) regulator, the method comprising:
 detecting a target current flowing through a sample transistor connected between an input node to which an input voltage is applied and a first node to which an output voltage is applied;   outputting a target code corresponding to the target current based on the target current;   determining a limit code based on the target code and a preset maximum current; and   outputting a control code that controls at least some of a plurality of power transistors connected between the input node and an output node within a range defined by the limit code such that an output current equal to an aim current flows through the output node to which the output voltage is applied.   
     
     
         12 . The method of  claim 11 , wherein determining the target code includes:
 detecting a target voltage corresponding to the target current based on the target current; and   converting the target voltage into the target code in digital format by using an analog-to-digital converter (ADC).   
     
     
         13 . The method of  claim 11 , wherein determining the limit code includes:
 identifying the target current based on the target code;   calculating a maximum number of transistors to be turned on among the plurality of power transistors based on the target current and the maximum current; and   determining the limit code corresponding to the maximum number.   
     
     
         14 . The method of  claim 13 , wherein outputting the control code includes:
 comparing the output voltage with a first reference voltage by using a first comparator;   decreasing the control code by a unit code in response to a first decrease signal output from the first comparator when the output voltage is greater than the first reference voltage; and   increasing the control code by the unit code within the range defined by the limit code in response to a first increase signal output from the first comparator when the output voltage is less than the first reference voltage.   
     
     
         15 . The method of  claim 14 , wherein outputting the control code further includes:
 comparing the output voltage with a second reference voltage by using a second comparator; and   increasing the control code by an integer multiple of the unit code within the range defined by the limit code in response to a second increase signal output from the second comparator when the output voltage is less than the second reference voltage.   
     
     
         16 . A semiconductor device including a low-dropout (LDO) regulator that operates based on a digital code, the semiconductor device comprising:
 a plurality of power transistors connected between an input node and an output node;   a first comparator configured to compare an output voltage applied to the output node with a first reference voltage, and output a first control signal based on a first comparison result obtained by comparing the output voltage with the first reference voltage;   a controller configured to output a control code that turns on at least some of the plurality of power transistors based on the first control signal such that an output current equal to an aim current is output through the output node; and   a current limit circuit configured to detect a target current output from a sample transistor connected to the input node and output a target code corresponding to the target current,   wherein the controller is further configured to determine a limit code based on the target code and a preset maximum current, and output the control code within a range defined by the limit code.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the current limit circuit includes:
 a sensing circuit configured to detect the target current;   a converting circuit configured to convert the target current into a target voltage corresponding to the target current; and   an analog-to-digital converter (ADC) configured to convert the target voltage into the target code.   
     
     
         18 . The semiconductor device of  claim 16 , wherein the controller is further configured to:
 identify the target current based on the target code;   calculate a maximum number of transistors to be turned on among the plurality of power transistors based on the target current and the maximum current; and   output the control code within the range defined by the limit code corresponding to the maximum number, and turn on a number of transistors, among the plurality of transistors, less than or equal to the maximum number, in response to the outputted control code.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the controller is further configured to:
 decrease a size of the control code by a unit code in response to a first decrease signal output from the first comparator when the output voltage is greater than the first reference voltage; and   increase the size of the control code by the unit code within the range defined by the limit code in response to a first increase signal output from the first comparator when the output voltage is less than the first reference voltage.   
     
     
         20 . The semiconductor device of  claim 19 , further comprising:
 a second comparator configured to compare the output voltage with a second reference voltage that is lower than the first reference voltage, and output a second control signal based on a second comparison result obtained by comparing the output voltage with the second reference voltage,   wherein the controller is further configured to increase the size of the control code by an integer multiple of the unit code within the range defined by the limit code in response to a second increase signal output from the second comparator when the output voltage is lower than the second reference voltage.