Riveted edge core for semiconductor packaging

Abstract

Architectures and process flows for a riveted edge core component for semiconductor packaging. The core component includes a glass core defined by a planar area enclosed by one or more edges that are substantially orthogonal to the planar area and at least one through-glass via (TGV) in the layer of glass, substantially filled with a conductive material. The core component has a cavity extending laterally within at least one of the one or more edges. A dielectric material is in the cavity. The cavity is defined by a first sidewall extending at a first angle from an edge of the layer of glass towards a center point, and a second sidewall extending at a second angle from the edge of the layer of glass towards the center point. The first angle and the second angle are less than 45 degrees.

What is claimed is: 
     
         1 . A substrate package component, comprising:
 a layer of glass comprising a rectangular prism volume defined by a planar area enclosed by one or more edges that are substantially orthogonal to the planar area;   a through-glass via (TGV) in the layer of glass, the TGV substantially filled with a conductive material;   a cavity extending laterally within at least one of the one or more edges; and   a dielectric material in the cavity.   
     
     
         2 . The substrate package component of  claim 1 , wherein:
 the layer of glass comprises a thickness;   the cavity is defined by a first sidewall extending at a first angle from an upper surface of the layer of glass towards a center point, and a second sidewall extending at a second angle from a lower surface of the layer of glass towards the center point; and   wherein the first angle is less than 85 degrees, and the second angle is less than 85 degrees.   
     
     
         3 . The substrate package component of  claim 2 , wherein the first angle is less than 45 degrees, and the second angle is less than 45 degrees. 
     
     
         4 . The substrate package component of  claim 1 , wherein the layer of glass has a thickness in a range of 20 microns+/−20% to 2 millimeters+/−20%. 
     
     
         5 . The substrate package component of  claim 1 , wherein:
 a first edge of the one or more edges has a length in a range of 10 millimeters (mm)+/−20% to 250 mm+/−20%; and   a second edge of the one or more edges is perpendicular to the first edge and has the length in a range of 10 mm+/−20% to 250 mm+/−20%.   
     
     
         6 . The substrate package component of  claim 1 , further comprising a first layer of the dielectric material on an upper surface of the layer of glass and a second layer of the dielectric material on a lower surface of the layer of glass, and wherein the first layer of the dielectric material, the second layer of the dielectric material, and the dielectric material in the cavity are contiguous. 
     
     
         7 . The substrate package component of  claim 1 , wherein the TGV is one of a plurality of TGVs that are patterned in the layer of glass and substantially filled with the conductive material. 
     
     
         8 . A substrate package, comprising:
 a first dielectric layer comprising a plurality of first redistribution layers (RDL) therein;   a layer of glass under the first dielectric layer, the layer of glass defined by a planar area enclosed by one or more perimeter edges that are substantially orthogonal to the planar area;   wherein the layer of glass comprises at least 23 percent Silicon and at least 26 percent Oxygen by weight, and at least 5 percent Aluminum by weight; a through-glass via (TGV) substantially filled with a conductive material; one or more cavities extending laterally within at least one of the one or more perimeter edges; and a mold material in the one or more cavities;   a second dielectric layer below the layer of glass, the second dielectric layer comprising a plurality of second RDL therein; and   at least one electrical path from an upper surface of the first dielectric layer through the TGV to a lower surface of the second dielectric layer.   
     
     
         9 . The substrate package of  claim 8 , wherein:
 the layer of glass comprises a thickness measured in a first direction; and   individual cavities of the one or more cavities are stacked in the first direction;   wherein individual cavities are defined by a first sidewall extending at a first angle of less than 85 degrees from a perimeter edge of the layer of glass towards a center point, and a second sidewall extending at a second angle of less than 85 degrees from the perimeter edge of the layer of glass towards the center point.   
     
     
         10 . The substrate package of  claim 9 , wherein the first angle is less than 45 degrees, and the second angle is less than 45 degrees. 
     
     
         11 . The substrate package of  claim 8 , wherein the layer of glass has a thickness in a range of 20 microns+/−20% to 2 millimeters+/−20%. 
     
     
         12 . The substrate package of  claim 8 , wherein:
 a first edge of the one or more perimeter edges has a length in a range of 10 millimeters (mm)+/−20% to 250 mm+/−20%; and   a second edge of the one or more perimeter edges is perpendicular to the first edge and has a length in a range of 10 mm+/−20% to 250 mm+/−20%.   
     
     
         13 . The substrate package of  claim 8 , further comprising:
 an integrated circuit (IC) die attached on the upper surface of the first dielectric layer; and   an encapsulant overlaid across the IC die.   
     
     
         14 . The substrate package of  claim 13 , further comprising solder bumps attached to the lower surface of the second dielectric layer. 
     
     
         15 . The substrate package of  claim 8 , further comprising:
 a first layer of the mold material between the first dielectric layer and the layer of glass;   a second layer of the mold material between the layer of glass and the second dielectric layer; and   wherein the first layer of the mold material, the second layer of the mold material, and the mold material in the one or more cavities are contiguous.   
     
     
         16 . The substrate package of  claim 15 , further comprising:
 an integrated circuit (IC) die attached on the upper surface of the first dielectric layer; and   solder bumps attached to the lower surface of the second layer.   
     
     
         17 . A system, comprising:
 the substrate package of  claim 14 ; and   a printed circuit board attached to the solder bumps.   
     
     
         18 . A method, comprising:
 etching a first top side of a first layer of glass to create a first high taper edge from the first top side to a first bottom side;   etching a second top side of a second layer of glass to create a second high taper edge from the second top side to a second bottom side;   fusing the first top side to the second top side to thereby create a glass core with a riveted edge;   patterning the glass core with the riveted edge with through-glass vias (TGVs) and redistribution layers to thereby create a unit;   reconstituting the unit with a plurality of similar units thereby creating a panel, wherein reconstituting includes at least partially filling the riveted edge with a mold material.   
     
     
         19 . The method of  claim 18 , further comprising:
 adding dielectric layers and additional redistribution layers to the units.   
     
     
         20 . The method of  claim 19 , further comprising singulating the panel into discrete systems.