Buffered dynamic random access memory device

Abstract

A DRAM device may be configured to retransmit or not retransmit zero or more of command/address signals, write data signals, read data signals, and/or data strobe signals. The DRAM device may have separate, unidirectional read data signal and write data signal interfaces. Combined activate and read or write commands may be implemented. The configuration of the DRAM to retransmit or not retransmit signals may be determined by the DRAM device's physical location on a module via hardwired configuration pins. The various configurations allows a DRAM device to be used on both a long and narrow form factor module and a DIMM module.

1 . (canceled) 
     
     
         2 . A memory module, comprising:
 a data interface;   a first rank comprising a first plurality of memory devices, the first rank to receive first write data and second write data via the data interface, and the first rank to transmit first read data via the data interface, the first write data to be received by the first rank for storage by the first plurality of memory devices, the second write data to, based on configuration information, be transmitted by the first rank to a second rank;   the second rank comprising a second plurality of memory devices, the second rank to receive the second write data for storage by the second plurality of memory devices and to transmit second read data to the first rank for transmission via the data interface;   a plurality of write data interconnection groups to respectively couple proper subsets of write data signals communicating the second write data from respective ones of the first plurality of memory devices to corresponding ones of the second plurality of memory devices; and   a plurality of read data interconnection groups to respectively couple proper subsets of read data signals communicating the second read data from respective ones of the second plurality of memory devices to corresponding ones of the first plurality of memory devices.   
     
     
         3 . The memory module of  claim 2 , wherein the proper subsets of write data signals are mutually disjoint non-overlapping portions of a wider write data bus coupled with the data interface. 
     
     
         4 . The memory module of  claim 3 , wherein the proper subsets of read data signals are mutually disjoint non-overlapping portions of a wider read data bus coupled with the data interface. 
     
     
         5 . The memory module of  claim 2 , further comprising:
 a command/address (CA) interface;   a first plurality of CA interconnections to couple CA signals received via the CA interface to the first plurality of memory devices; and   a second plurality of CA interconnections to couple CA signals received from a first one of the first plurality of memory devices to the second plurality of memory devices, the first one of the first plurality of memory devices to transmit the CA signals received via the CA interface to the second plurality of memory devices via the second plurality of CA interconnections.   
     
     
         6 . The memory module of  claim 2 , wherein the second write data is to be transmitted by the first rank to the second rank further based on a write access being directed to the second rank, and wherein the second read data is to be transmitted by the first rank based on a read access being directed to the second rank. 
     
     
         7 . The memory module of  claim 2 , wherein, based on the configuration information, at least one of the first plurality of memory devices is to retransmit a data strobe (DQS) signal received from the second rank. 
     
     
         8 . The memory module of  claim 2 , wherein, based on the configuration information, at least one of the first plurality of memory devices is to internally generate a data strobe (DQS) signal and is to transmit the DQS signal. 
     
     
         9 . A memory device for a first rank of a memory module, the memory device comprising:
 a first data interface to receive a proper subset of write data signals transmitted by a controller;   a second data interface to, based on configuration information, transmit the proper subset of write data signals to a corresponding memory device in a second rank;   a third data interface to receive a proper subset of read data signals transmitted by the second rank from the corresponding memory device; and   a fourth data interface to, based on the configuration information, transmit the proper subset of read data signals transmitted by the second rank to the controller.   
     
     
         10 . The memory device of  claim 9 , further comprising a multiplexer to select, for transmission to the controller, between the proper subset of read data signals received from the corresponding memory device and read data from a memory array of the memory device. 
     
     
         11 . The memory device of  claim 9 , wherein, based on the configuration information, a DQS signal received from the second rank is to be transmitted, by the memory device, to the controller. 
     
     
         12 . The memory device of  claim 9 , wherein, based on the configuration information, a DQS signal generated by the memory device is to be transmitted, by the memory device, to the controller. 
     
     
         13 . The memory device of  claim 9 , further comprising:
 a DQS multiplexer; and   DQS generation circuitry, the DQS multiplexer to select, for transmission to the controller, between a DQS signal received from the second rank and a DQS signal generated by the DQS generation circuitry.   
     
     
         14 . The memory device of  claim 9 , wherein the configuration information is indicated by values written to configuration registers via at least one of:
 command/address signals, mode register set commands, a serial presence detect interface, and the first data interface.   
     
     
         15 . The memory device of  claim 9 , further comprising:
 a first CA interface to receive CA signals transmitted by the controller; and   a second interface to, based on the configuration information, transmit the CA signals received via the first CA interface to the second rank.   
     
     
         16 . A method of operating a memory module, comprising:
 receiving, by a first rank comprising a first plurality of memory devices, first write data and second write data via a data interface of the memory module;   transmitting, by the first rank, first read data via the data interface;   storing, by the first plurality of memory devices, proper subsets of the first write data in respective ones of the first plurality of memory devices;   transmitting, based on configuration information and by the first rank, the second write data to a second rank, the second rank comprising a second plurality of memory devices;   receiving, by the second plurality of memory devices, the second write data from the first rank;   storing, by the second plurality of memory devices, proper subsets of the second write data in respective ones of the second plurality of memory devices;   transmitting, by the second plurality of memory devices and to the first rank, second read data; and   transmitting, based on the configuration information and by the first rank, the second read data via the data interface.   
     
     
         17 . The method of  claim 16 , wherein the proper subsets of the first write data correspond to mutually disjoint non-overlapping portions of a wider write data bus coupled with the data interface of the memory module. 
     
     
         18 . The method of  claim 16 , wherein the proper subsets of the second write data correspond to the proper subsets of the first write data. 
     
     
         19 . The method of  claim 16 , further comprising:
 receiving, via a command/address interface of the memory module, a first access command directed to the first rank and a second access command directed to the second rank.   
     
     
         20 . The method of  claim 19 , further comprising:
 based on the first access command being directed to the first rank, performing, by the first plurality of memory devices, the first access command.   
     
     
         21 . The method of  claim 20 , further comprising:
 based on the second access command being directed to the second rank, transmitting, by at least one of the first plurality of memory devices and to at least one of the second plurality of memory devices, the second access command.