Semiconductor system and method for operating the same

Abstract

A semiconductor system and a method for operating the semiconductor system are provided. The semiconductor system comprises a duty cycle corrector (DCC) and an analog quadrature error corrector (QEC). The DCC is configured to receive an input clock signal to adjust a duty cycle of the input clock signal and generate a first modified clock signal. The analog QEC is configured to receive the first modified clock signal. The analog QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal. The second output clock signal delays or advances a quarter of period from the first output clock signal. The analog QEC comprises a first inverter chain, a phase error detector (PED) and a first low-pass filter (LPF).

What is claimed is: 
     
         1 . A semiconductor system, comprising:
 a duty cycle corrector (DCC) configured to receive an input clock signal, wherein the DCC is configured to adjust a duty cycle of the input clock signal and generate a first modified clock signal; and   an analog quadrature error corrector (analog QEC) configured to receive the first modified clock signal, wherein the analog QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal, and the second output clock signal delays or advances a quarter of period from the first output clock signal, wherein the analog QEC comprises:
 a first inverter chain comprising a plurality of inverters, configured to receive the first modified clock signal and generate the first output clock signal; 
 a phase error detector (PED) configured to receive the first output clock signal and adjust a phase of the first output clock signal; and 
 a first low-pass filter (LPF) electrically connected to the PED and configured to filter the first output clock signal having the adjusted phase. 
   
     
     
         2 . The semiconductor system of  claim 1 , wherein the analog QEC further comprises:
 a second inverter chain comprising a plurality of inverters, configured to receive the first modified clock signal and generate the second output clock signal; and   a first operational amplifier (OP), electrically connected between the first LPF and the second inverter chain.   
     
     
         3 . The semiconductor system of  claim 2 , wherein the first inverter chain further comprises a plurality of first transistors, each of the first transistors is electrically coupled between two adjacent inverters of the first inverter chain, and the first transistors are operable in response to a reference voltage. 
     
     
         4 . The semiconductor system of  claim 3 , wherein the second inverter chain further comprises a plurality of second transistors, each of the plurality of second transistors is electrically coupled between two adjacent inverters of the second inverter chain, and the second transistors are operable in response to an output voltage of the first OP. 
     
     
         5 . The semiconductor system of  claim 1 , wherein the DCC further comprises:
 a duty-altering circuit configured to alter the duty cycle of the input clock signal;   a second operational amplifier (OP) electrically connected to the duty-altering circuit; and   a second low-pass filter (LPF) electrically connected to the second OP.   
     
     
         6 . The semiconductor system of  claim 5 , wherein the DCC is an analog DCC, the first output clock signal output by a last inverter of the first inverter chain is configured to be transmitted to the second LPF, a pre-output clock signal output by a second-to-last inverter of the first inverter chain is configured to be transmitted to the second LPF, the second-to-last inverter is a previous stage of the last inverter, and the pre-output clock signal delays or advances half of period from the first output clock signal. 
     
     
         7 . The semiconductor system of  claim 6 , further comprising a first signal divider configured to receive the first output clock signal and generate two additional output signals, wherein one of the additional output signals delays or advances half of period from the other of the additional output signals. 
     
     
         8 . The semiconductor system of  claim 5 , wherein the DCC is an analog DCC, and the analog DCC further comprises a second signal divider electrically connected between the duty-altering circuit and the second LPF, the second signal divider is configured to receive the input clock signal with altered duty cycle from the duty-altering circuit and generate the first modified clock signal and a second modified clock signal, wherein the second modified clock signal delays or advances half of period from the first modified clock signal. 
     
     
         9 . A semiconductor system, comprising:
 a duty cycle corrector (DCC) configured to receive an input clock signal, wherein the DCC is configured to adjust a duty cycle of the input clock signal and generate a first modified clock signal; and   a digital quadrature error corrector (digital QEC) configured to receive the first modified clock signal, wherein the digital QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal, and the second output clock signal delays or advances a quarter of period from the first output clock signal, wherein the digital QEC comprises:
 a first inverter chain comprising a plurality of inverters, configured to receive the first modified clock signal and generate the first output clock signal; 
 a digital phase error detector (DPED) configured to receive the first output clock signal and adjust a phase of the first output clock signal; and 
 a finite state machine (FSM) electrically connected to the DPED and configured to receive the first output clock signal having the adjusted phase. 
   
     
     
         10 . The semiconductor system of  claim 9 , wherein the digital QEC further comprises a second inverter chain comprising a plurality of inverters, configured to receive the first modified clock signal and generate the second output clock signal. 
     
     
         11 . The semiconductor system of  claim 10 , wherein the first inverter chain further comprises a plurality of first capacitors, each of the first capacitors is electrically coupled between two adjacent inverters of the first inverter chain. 
     
     
         12 . The semiconductor system of  claim 11 , wherein the second inverter chain further comprises a plurality of second capacitors, each of the plurality of second capacitors is electrically coupled between two adjacent inverters of the second inverter chain. 
     
     
         13 . The semiconductor system of  claim 11 , wherein the DCC further comprises:
 a duty-altering circuit configured to alter the duty cycle of the input clock signal;   an operational amplifier (OP) electrically connected to the duty-altering circuit; and   a low-pass filter (LPF) electrically connected to the OP.   
     
     
         14 . The semiconductor system of  claim 13 , wherein the DCC is an analog DCC, the first output clock signal output by a last inverter of the first inverter chain is configured to be transmitted to the LPF. 
     
     
         15 . The semiconductor system of  claim 14 , wherein a pre-output clock signal output by a second-to-last inverter of the first inverter chain is configured to be transmitted to the LPF, the second-to-last inverter is a previous stage of the last inverter, and the pre-output clock signal delays or advances half of period from the first output clock signal. 
     
     
         16 . The semiconductor system of  claim 15 , further comprising a first signal divider configured to receive the first output clock signal and generate two additional output signals, wherein one of the additional output signals delays or advances half of period from the other of the additional output signals. 
     
     
         17 . The semiconductor system of  claim 13 , wherein the DCC is an analog DCC, the analog DCC further comprises a buffering circuit electrically connected to the duty-altering circuit, and the buffering circuit is configured to receive the input clock signal with altered duty cycle and generate the first modified clock signal. 
     
     
         18 . The semiconductor system of  claim 14 , wherein the DCC is an digital DCC, and the digital DCC comprises:
 the duty-altering circuit configured to alter the duty cycle of the input clock signal; and   a second signal divider configured to receive the input clock signal with altered duty cycle and generate the first modified clock signal and a second modified clock signal, wherein second modified clock signal delays or advances half of period from the first modified clock signal.   
     
     
         19 . A method for operating a semiconductor system, comprising:
 receiving an input clock signal;   adjusting a duty cycle of the input clock signal to generate a first modified clock signal;   receiving the first modified clock signal;   adjusting a delay of the first modified clock signal to generate a first output clock signal and a second output clock signal; and   receiving the first output clock signal and adjusting a phase of the first output clock signal.   
     
     
         20 . The method of  claim 19 , further comprising delaying or advancing a quarter of period from the first output clock signal by the second output clock signal.