Reducing read disturbance overestimation

Abstract

Methods, systems, and devices for reducing read disturbance overestimation are described. A memory system may maintain a bitmap associated with a virtual block, where the virtual block may be associated with first blocks across multiple dies and each bit of the bitmap may correspond to a respective first block of each die. The memory system may perform a first read operation at the first block of a first die and, accordingly, may set a first bit of the bitmap to a first value. The memory system may determine whether to adjust a read counter associated with the virtual block based on values within the bitmap. For example, the memory system may adjust the read counter based on determining that each bit of the bitmap is set to the first value or based on performing a second read operation on the first block of the first die.

What is claimed is: 
     
         1 . A memory system, comprising:
 one or more memory devices; and   processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
 perform a first read operation at a first block of a first memory die of a set of memory dies, a respective first block of each memory die of the set of memory dies being associated with a virtual block; 
 set a first bit of a bitmap to a first value in response to performing the first read operation, wherein the bitmap is associated with the virtual block and wherein the first bit of the bitmap corresponds to the first block of the first memory die; and 
 determine whether to adjust a read counter associated with the virtual block in accordance with respective values of each bit of the bitmap. 
   
     
     
         2 . The memory system of  claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
 adjust the read counter in response to determining that each bit of the bitmap is set to the first value.   
     
     
         3 . The memory system of  claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
 perform, in response to performing the first read operation, a second read operation at the first block of the first memory die; and   adjust the read counter in response to determining that the first bit of the bitmap is set to the first value and on performing the second read operation at the first block of the first memory die.   
     
     
         4 . The memory system of  claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
 reset the bitmap in response to determining to adjust the read counter associated with the virtual block.   
     
     
         5 . The memory system of  claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
 refrain from adjusting the read counter in response to determining that each bit of the bitmap is not set to the first value.   
     
     
         6 . The memory system of  claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
 perform one or more refresh operations on the respective first blocks of each memory die of the set of memory dies in response to the read counter satisfying a threshold.   
     
     
         7 . The memory system of  claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
 perform a second read operation at a second block of the first memory die of the set of memory dies, a respective second block of each memory die of the set of memory dies being associated with a second virtual block;   set a first bit of a second bitmap to the first value in response to performing the second read operation, wherein the second bitmap is associated with the second virtual block and the first bit of the second bitmap corresponds to the second block of the first memory die of the set of memory dies; and   determine whether to adjust a second read counter associated with the second virtual block in accordance with respective values of each bit of the second bitmap.   
     
     
         8 . The memory system of  claim 7 , wherein the processing circuitry is further configured to cause the memory system to:
 adjust the second read counter in response to determining that each bit of the second bitmap is set to the first value.   
     
     
         9 . The memory system of  claim 1 , wherein each bit of the bitmap corresponds to a respective first block of each memory die of the set of memory dies, and wherein each respective first block of each memory die of the set of memory dies comprises a same block index. 
     
     
         10 . The memory system of  claim 1 , wherein the bitmap is stored in volatile memory of the memory system. 
     
     
         11 . A memory system, comprising:
 one or more memory devices; and   processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
 perform a first read operation at a first block of a first plane of a set of planes, wherein a respective first block of each plane of the set of planes is associated with a virtual block; 
 set a first bit of a bitmap to a first value in response to performing the first read operation, wherein the bitmap is associated with the virtual block and wherein the first bit of the bitmap corresponds to the first block of the first plane of the set of planes; and 
 determine whether to adjust a read counter associated with the virtual block in accordance with respective values of each bit of the bitmap. 
   
     
     
         12 . The memory system of  claim 11 , wherein the processing circuitry is further configured to cause the memory system to:
 adjust the read counter in response to determining that each bit of the bitmap is set to the first value.   
     
     
         13 . The memory system of  claim 11 , wherein the processing circuitry is further configured to cause the memory system to:
 perform, in response to performing the first read operation, a second read operation at the first block of the first plane; and   adjust the read counter in response to determining that the first bit of the bitmap is set to the first value and on performing the second read operation at the first block of the first plane.   
     
     
         14 . The memory system of  claim 11 , wherein the processing circuitry is further configured to cause the memory system to:
 reset the bitmap in response to determining to adjust the read counter associated with the virtual block.   
     
     
         15 . The memory system of  claim 11 , wherein the processing circuitry is further configured to cause the memory system to:
 refrain from adjusting the read counter in accordance with determining that at each bit of the bitmap is set not to the first value.   
     
     
         16 . The memory system of  claim 11 , wherein the processing circuitry is further configured to cause the memory system to:
 perform one or more refresh operations on the respective first blocks of each plane of the set of planes in response to the read counter satisfying a threshold.   
     
     
         17 . The memory system of  claim 11 , wherein the processing circuitry is further configured to cause the memory system to:
 perform a second read operation at a second block of the first plane, wherein respective second blocks of each plane of the set of planes are associated with a second virtual block;   set a first bit of a second bitmap to the first value in response to performing the second read operation, wherein the second bitmap is associated with the second virtual block and the first bit of the second bitmap corresponds to the second block of the first plane; and   determine whether to adjust a second read counter associated with the second virtual block in accordance with respective values of each bit of the second bitmap.   
     
     
         18 . The memory system of  claim 17 , wherein the processing circuitry is further configured to cause the memory system to:
 adjust the second read counter in response to determining that each bit of the second bitmap is set to the first value.   
     
     
         19 . The memory system of  claim 11 , wherein each bit of the bitmap corresponds to a respective first block of each plane of the set of planes, and wherein each respective first block of each plane of the set of planes comprises a same block index. 
     
     
         20 . The memory system of  claim 11 , wherein:
 each plane of the set of planes are included in a memory die,   a first subset of the set of planes are included in a first memory die and a second subset of the set of planes are included in a second memory die, or   each plane of the set of planes are included in a respective memory die of the memory system.   
     
     
         21 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system cause the memory system to:
 perform a first read operation at a first block of a first memory die of a set of memory dies, a respective first block of each memory die of the set of memory dies being associated with a virtual block;   set a first bit of a bitmap to a first value in response to performing the first read operation, wherein the bitmap is associated with the virtual block and wherein the first bit of the bitmap corresponds to the first block of the first memory die; and   determine whether to adjust a read counter associated with the virtual block in accordance with respective values of each bit of the bitmap.   
     
     
         22 . The non-transitory computer-readable medium of  claim 21 , wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to:
 adjust the read counter in response to determining that each bit of the bitmap is set to the first value.