Semiconductor device and method of fabricating the same

Abstract

Provided is a semiconductor device and method of manufacturing same, the semiconductor device including: a plurality of active patterns on a substrate; a source/drain pattern on the substrate; a power rail in the substrate; a pillar pattern between the plurality of active patterns; a channel pattern on the pillar pattern; a backside conductive contact between the source/drain pattern and the power rail; and a liner pattern on the pillar pattern, wherein the liner pattern includes: a first portion that covers a top surface of a lower portion of the backside conductive contact; and a second portion that extends from the first portion and along a sidewall of the lower portion of the backside conductive contact.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a plurality of active patterns on a substrate;   a source/drain pattern on the substrate;   a power rail in the substrate;   a pillar pattern between the plurality of active patterns;   a channel pattern on the pillar pattern;   a backside conductive contact between the source/drain pattern and the power rail; and   a liner pattern on the pillar pattern,   wherein the liner pattern comprises:
 a first portion that covers a top surface of a lower portion of the backside conductive contact; and 
 a second portion that extends from the first portion and along a sidewall of the lower portion of the backside conductive contact. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the second portion of the liner pattern separates the pillar pattern from the lower portion of the backside conductive contact. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the second portion of the liner pattern is between the pillar pattern and the lower portion of the backside conductive contact. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the second portion of the liner pattern covers a lateral surface of a lower portion of the pillar pattern. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the second portion of the liner pattern extends from the first portion of the liner pattern to a top surface of the power rail. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the second portion of the liner pattern is in contact with the power rail. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the second portion of the liner pattern covers opposite lateral surfaces of the lower portion of the backside conductive contact. 
     
     
         8 . The semiconductor device of  claim 1 ,
 wherein the second portion of the liner pattern comprises a pair of second portions that neighbor each other in a first direction parallel to a top surface of the substrate, and   wherein the pair of second portions are connected to each other through the first portion of the liner pattern.   
     
     
         9 . The semiconductor device of  claim 1 , wherein the first portion of the liner pattern is between the plurality of active patterns and the lower portion of the backside conductive contact. 
     
     
         10 . The semiconductor device of  claim 1 , wherein a width of the pillar pattern decreases in a direction perpendicular to a top surface of the substrate. 
     
     
         11 . The semiconductor device of  claim 1 ,
 wherein the backside conductive contact comprises a plurality of backside conductive contacts that are disposed along a first direction parallel to a top surface of the substrate, and   wherein the pillar pattern is between the plurality of backside conductive contacts.   
     
     
         12 . The semiconductor device of  claim 1 , wherein the pillar pattern separates the plurality of active patterns from each other. 
     
     
         13 . A semiconductor device comprising:
 a plurality of active patterns on a substrate;   a source/drain pattern on the substrate;   a power rail in the substrate;   a pillar pattern between the plurality of active patterns;   a channel pattern on the pillar pattern;   a backside conductive contact between the source/drain pattern and the power rail; and   a liner pattern between the pillar pattern and a lower portion of the backside conductive contact.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the liner pattern separates the pillar pattern from the lower portion of the backside conductive contact. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the liner pattern covers a lateral surface of a lower portion of the pillar pattern. 
     
     
         16 . The semiconductor device of  claim 13 , wherein, between the pillar pattern and the lower portion of the backside conductive contact, the liner pattern extends between the plurality of active patterns and the lower portion of the backside conductive contact. 
     
     
         17 . The semiconductor device of  claim 13 , wherein the liner pattern comprises:
 a first portion that covers a top surface of the lower portion of the backside conductive contact; and   a second portion that extends from the first portion and along a sidewall of the lower portion of the backside conductive contact.   
     
     
         18 . The semiconductor device of  claim 13 , wherein the liner pattern covers opposite lateral surfaces of the lower portion of the backside conductive contact. 
     
     
         19 . The semiconductor device of  claim 13 , wherein the liner pattern extends to a top surface of the power rail from a bottom surface of one of the plurality of active patterns. 
     
     
         20 . A semiconductor device comprising:
 a plurality of active patterns on a substrate;   a source/drain pattern on the substrate;   a power delivery network layer on a bottom surface of the substrate;   a power rail in the substrate;   a pillar pattern between the plurality of active patterns;   a channel pattern on the pillar pattern;   a gate electrode between the plurality of semiconductor patterns;   a backside conductive contact between the source/drain pattern and the power rail; and   a liner pattern on the pillar pattern,   wherein the liner pattern comprises:
 a first portion that covers a top surface of a lower portion of the backside conductive contact; and 
 a second portion that extends from the first portion and along a sidewall of the lower portion of the backside conductive contact.