Memory device and method of manufacturing the same

Abstract

The present disclosure provides a method of manufacturing a memory device including forming a laminate including a first insulating layer and a first sacrificial layer sequentially laminated on the first insulating layer, a 1-1 gate insulating layer, a channel material layer, a 1-2 gate insulating layer, and a second sacrificial layer; patterning the laminate to form a patterned laminate having at least one pattern portion; forming a second recessed portion exposing the 1-1 and 1-2 gate insulating layers by recessing the first and second sacrificial layers in a capacitor formation area adjacent to the transistor formation area of the structure; defining a protruding channel portion from the channel material layer; and forming a capacitor in contact with the exposed upper, lower, and side surfaces of the protruding channel portion in the capacitor formation area.

What is claimed is: 
     
         1 . A method of manufacturing a memory device, comprising:
 forming a laminate including a first insulating layer and a first sacrificial layer sequentially laminated on the first insulating layer, a 1-1 gate insulating layer, a channel material layer, a 1-2 gate insulating layer, and a second sacrificial layer;   patterning the laminate to form a patterned laminate having at least one pattern portion, wherein the pattern portion has a shape extending in a first direction and an etched region is provided on both sides of the pattern portion along a second direction perpendicular to the first direction;   filling a separation material into the etched region on both sides of the at least one pattern portion to define a structure including at least the patterned laminate;   forming a first vertical hole penetrating the pattern portion in a transistor formation region of the structure and recessing the first and second sacrificial layers around the first vertical hole to form a first recess portion;   forming a word line in the first recess portion to define a transistor including the word line;   forming a bit line connected to the channel material layer in an area corresponding to the first vertical hole of the structure;   forming a second recessed portion exposing the 1-1 and 1-2 gate insulating layers by recessing the first and second sacrificial layers in a capacitor formation area adjacent to the transistor formation area of the structure;   defining a protruding channel portion from the channel material layer by recessing the channel material layer and the 1-1 and 1-2 gate insulating layers in the second recessed portion so that the protruding channel portion protruding into the second recessed portion remains and upper, lower, and side surfaces of the protruding channel portion are exposed; and   forming a capacitor in contact with the exposed upper, lower, and side surfaces of the protruding channel portion in the capacitor formation area.   
     
     
         2 . The method of  claim 1 , wherein the first insulating layer comprises silicon oxide, and the first and second sacrificial layers comprise silicon nitride. 
     
     
         3 . The method of  claim 1 , wherein the separation material has a different material composition from the first insulating layer and the first and second sacrificial layers. 
     
     
         4 . The method of  claim 1 , wherein the patterned laminate is formed to include a plurality of pattern portions spaced apart from each other in the second direction and a pattern connection portion connecting the plurality of pattern portions in the second direction. 
     
     
         5 . The method of  claim 1 ,
 wherein the word line includes a gate unit structure formed corresponding to the channel material layer of the transistor formation region,   wherein a plurality of the gate unit structures is arranged spaced apart from each other in the second direction, and the word line further includes a connection line portion connecting the plurality of gate unit structures in the second direction,   wherein the connection line portion is formed at a position corresponding to the pattern connection portion.   
     
     
         6 . The method of  claim 4 , before forming the bit line, further comprising:
 removing the separation material from the structure;   removing the channel material layer portion arranged in the pattern connection portion from the patterned laminate; and   filling a space around the plurality of pattern portions with a second separation material.   
     
     
         7 . The method of  claim 1 , the step of forming the word line to define the transistor comprises:
 forming a word line material layer filling at least a portion of the first vertical hole and the first recess portion in the transistor formation region;   forming a through hole by etching a region corresponding to the first vertical hole in the word line material layer;   forming a recess region by recessing a portion of the word line material layer exposed through the through hole so that one end of the channel material layer protrudes toward the through hole more than the word line material layer; and   forming a filling insulating layer in the recess region.   
     
     
         8 . The method of  claim 1 ,
 wherein the patterned laminate is formed to include a plurality of the pattern portions spaced apart from each other in the second direction and a pattern connection portion connecting the plurality of the pattern portions in the second direction,   wherein the step of forming the word line to define the transistor comprises:
 forming a word line material layer filling at least a portion of the first vertical hole and the first recess portion in the transistor formation region; 
 removing the separation material from the structure; 
 removing a portion of the channel material layer arranged in the pattern connection portion from the patterned laminate; 
 filling a space around the plurality of pattern portions with a second separation material; 
 forming a through hole by etching a region corresponding to the first vertical hole in the word line material layer; 
 forming a recess region by recessing a portion of the word line material layer exposed through the through hole so that one end of the channel material layer protrudes toward the through hole more than the word line material layer; and 
 forming a filling insulating layer within the recessed region. 
   
     
     
         9 . The method of  claim 1 , after forming an etched portion by etching the pattern portion in the capacitor formation region of the structure further comprising:
 forming the second recess portion injecting a wet etching solution through the etched portion.   
     
     
         10 . The method of  claim 1 , wherein the step of defining the protruding channel portion comprises:
 recessing the channel material layer in the second recessed portion; and   removing the 1-1 and 1-2 gate insulating layers from the second recessed portion.   
     
     
         11 . The method of  claim 1 , wherein the step of forming the capacitor includes:
 forming an electrode member in contact with the upper, lower, and side surfaces of the first protruding channel member on the inner surface of the second recessed portion;   forming a dielectric layer on the electrode member; and   forming a plate electrode on the dielectric layer.   
     
     
         12 . The method of  claim 1 , after forming the electrode member, further comprising:
 recessing the first insulating layer in the capacitor formation region to expose the outer surface of the electrode member is further included; and   sequentially forming the dielectric layer and the plate electrode after exposing the outer surface of the electrode member.   
     
     
         13 . The method of  claim 1 ,
 wherein the first insulating layer, the first sacrificial layer, the 1-1 gate insulating layer, the channel material layer, the 1-2 gate insulating layer, and the second sacrificial layer form one unit laminate,   wherein the unit laminate is repeatedly laminated on a substrate in the step of forming the laminate.   
     
     
         14 . The method of  claim 13 ,
 wherein the transistor is a first transistor, and the capacitor is a first capacitor,   wherein the memory device further includes a second transistor disposed on the first transistor and a second capacitor disposed on the first capacitor.   
     
     
         15 . A memory device comprising a plurality of memory cells stacked in a vertical direction, comprising:
 each of the plurality of memory cells includes a transistor and a capacitor electrically connected to the side of the transistor,   wherein the transistor includes a channel material layer, a word line disposed opposite the transistor, and a gate insulating layer disposed between them,   wherein the capacitor includes an electrode member electrically connected to the transistor, a dielectric layer disposed on a surface of the electrode member, and a plate electrode disposed on a surface of the dielectric layer,   wherein a bit line extending in a vertical direction is provided, which is connected to a plurality of transistors of the plurality of memory cells,   wherein the channel material layer includes a protruding channel portion protruding into a capacitor formation region, the electrode member is disposed to contact upper, lower, and side surfaces of the protruding channel portion,   wherein the word line includes a plurality of gate unit structures spaced apart from each other and a connection line portion connecting the plurality of gate unit structures.   
     
     
         16 . The device of  claim 15 ,
 wherein the electrode member has a structure that extends upwardly and laterally with respect to the protruding channel portion while contacting the upper surface and side surfaces of the protruding channel portion,   wherein the dielectric layer is arranged to contact the inner surface and the outer surface of the electrode member,   wherein the plate electrode is arranged to contact the dielectric layer while filling the inner space and the outer space of the electrode member.   
     
     
         17 . The device of  claim 15 ,
 wherein the plurality of gate unit structures is arranged between the plurality of bit lines and the plurality of capacitors,   wherein the connection line portion is arranged to have a narrower width than each of the plurality of gate unit structures and to connect the plurality of gate unit structures in the extension direction of the word line.   
     
     
         18 . The device of  claim 15 ,
 wherein the plurality of gate unit structures are arranged on each of the two sides of the bit line,   wherein the memory device in which the connection line portion is arranged on each of the two sides of the bit line.   
     
     
         19 . The device of  claim 15 , wherein the gate unit structure has a concave side surface when viewed from above toward the bit line. 
     
     
         20 . The device of  claim 15 ,
 wherein a sacrificial insulating layer is disposed between each of the plurality of gate unit structures and the electrode member corresponding thereto,   wherein a separation material film composed of a different material from the sacrificial insulating layer is disposed between the plurality of gate unit structures.