High bandwidth memory with sub 4f2 cells

Abstract

A semiconductor device, including a plurality of DRAM devices vertically stacked; a through silicon via (TSV) vertically penetrating the plurality of DRAM devices; a conductive pad electrically connecting the plurality of DRAM devices; and a protective layer located on an upper surface of the DRAM device formed to enclose the TSV, wherein the DRAM device includes a substrate; a plurality of bit lines located on the substrate, and disposed parallel to each other in a first horizontal direction at predetermined intervals; a plurality of word lines located on the bit line, and disposed parallel to each other in a second horizontal direction substantially perpendicular to the first horizontal direction at predetermined intervals; a plurality of channel patterns arranged in a honeycomb structure on the bit line; and a gate insulating pattern located between the plurality of channel patterns and the plurality of word lines.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a plurality of DRAM devices vertically stacked;   a through silicon via (TSV) vertically penetrating the plurality of DRAM devices;   a conductive pad electrically connecting the plurality of DRAM devices; and   a protective layer located on an upper surface of the DRAM device formed to enclose the TSV,   wherein the DRAM device comprises:   a substrate;   a plurality of bit lines located on the substrate, and disposed parallel to each other in a first horizontal direction at predetermined intervals;   a plurality of word lines located on the bit line, and disposed parallel to each other in a second horizontal direction substantially perpendicular to the first horizontal direction at predetermined intervals;   a plurality of channel patterns arranged in a honeycomb structure on the bit line, the plurality of channel patterns each extending in a vertical direction; and   a gate insulating pattern located between the plurality of channel patterns and the plurality of word lines;   wherein the plurality of word lines comprise a first word line and a second word line respectively disposed at different heights, and the first and second word lines are provided alternating with each other in the first horizontal direction, and   the plurality of channel patterns located on the single bit line are arranged in zigzag along both edges of the single bit line, and the plurality of channel patterns contacting the single word line are arranged in a straight line.   
     
     
         2 . The semiconductor device of  claim 1 , wherein at least a portion of each channel pattern is in direct contact with the substrate. 
     
     
         3 . The semiconductor device of  claim 1 , wherein each of the plurality of channel patterns comprises an upper electrode and a lower electrode, and the lower electrode is in contact with the bit line. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising a gate electrode arranged between the word line and the gate insulating pattern. 
     
     
         5 . A semiconductor package, comprising:
 a package substrate;   an interposer mounted on the package substrate;   a processor chip mounted on the interposer; and   the semiconductor device of  claim 1  mounted on the interposer, spaced apart from the processor chip.   
     
     
         6 . The semiconductor package of  claim 1 , wherein the semiconductor device and the processor chip further comprise a physical layer.