Memory device and method of forming same

Abstract

A method of manufacturing a semiconductor device includes forming a stack that includes channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack across the fin-shaped structure, selectively removing the sacrificial layers to release the channel layers as channel members, depositing a dummy layer in space between the channel members, removing the dummy gate stack, removing the dummy layer, forming a gate structure to wrap around each of the channel members, depositing a backside dielectric layer on a backside of the semiconductor device, patterning the backside dielectric layer to form a backside gate via opening directly under the gate structure, doping a threshold voltage tuning dopant into the gate structure through the backside gate via opening, and after the doping of the threshold voltage tuning dopant, forming a backside gate via in the backside gate via opening.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, comprising:
 forming over a substrate a stack that includes channel layers interleaved by sacrificial layers;   patterning the stack to form a fin-shaped structure;   forming a dummy gate stack over a channel region of the fin-shaped structure;   depositing a gate spacer layer over the dummy gate stack;   after the depositing of the gate spacer layer, recessing a source/drain region of the fin-shaped structure;   selectively removing the sacrificial layers in the channel region to release the channel layers as channel members;   depositing a dummy layer in space between the channel members;   selectively and partially recessing the dummy layer to form inner spacer recesses;   forming inner spacers in the inner spacer recesses;   forming a source/drain feature over the source/drain region;   removing the dummy gate stack;   removing the dummy layer;   forming a gate structure to wrap around each of the channel members, the gate structure including a gate dielectric layer and a gate electrode layer;   depositing a backside dielectric layer on a backside of the semiconductor device;   patterning the backside dielectric layer to form a backside gate via opening directly under the gate structure;   doping a threshold voltage tuning dopant into the gate electrode layer of the gate structure through the backside gate via opening; and   after the doping of the threshold voltage tuning dopant, forming a backside gate via in the backside gate via opening.   
     
     
         2 . The method of  claim 1 , wherein the semiconductor device is a memory device including at least a first memory cell and a second memory cell abutting the first memory cell, and the gate structure is part of a first pass-gate transistor in the first memory cell. 
     
     
         3 . The method of  claim 2 , wherein the gate structure is shared with a second pass-gate transistor in the second memory cell. 
     
     
         4 . The method of  claim 1 , wherein the threshold voltage tuning dopant is selected from fluorine, oxygen, hydrogen, or nitrogen. 
     
     
         5 . The method of  claim 1 , wherein a peak of a concentration of the threshold voltage tuning dopant is positioned directly above the backside gate via. 
     
     
         6 . The method of  claim 1 , further comprising:
 performing an annealing to diffuse the threshold voltage tuning dopant into a work function metal layer of the gate electrode layer.   
     
     
         7 . The method of  claim 1 , further comprising:
 depositing an isolation feature on sidewalls of the fin-shaped structure;   depositing a hard mask layer over the isolation feature;   extending the backside gate via opening through the isolation feature in a first etching process; and   extending the backside gate via opening through the hard mask layer in a second etching process different from the first etching process.   
     
     
         8 . The method of  claim 7 , further comprising:
 after the extending of the backside gate via opening through the hard mask layer, extending the backside gate via opening through the gate dielectric layer to expose the gate electrode layer of the gate structure.   
     
     
         9 . The method of  claim 1 , further comprising:
 depositing a frontside dielectric layer on a frontside of the semiconductor device;   patterning the frontside dielectric layer to form a frontside gate via opening directly above the gate structure; and   forming a frontside gate via in the frontside gate via opening.   
     
     
         10 . The method of  claim 9 , further comprising:
 prior to the forming of the frontside gate via, diffusing the threshold voltage tuning dopant into the gate electrode layer of the gate structure through the frontside gate via opening.   
     
     
         11 . A method of manufacturing a semiconductor device, comprising:
 forming first and second active regions protruding from a substrate;   depositing a first gate across the first and second active regions to form a first transistor and a second transistor;   depositing a second gate across the first active region to form a third transistor;   depositing a third gate across the second active region in forming a fourth transistor;   depositing a dielectric layer covering the first, second, and third gates;   forming a gate via opening through the dielectric layer and exposing the first gate;   doping a threshold voltage tuning dopant into the first gate through the gate via opening; and   forming a gate via in the gate via opening.   
     
     
         12 . The method of  claim 11 , wherein the first transistor is a pass-gate transistor of a first memory cell, the second transistor is a pull-down transistor of the first memory cell, the third transistor is a pass-gate transistor of a second memory cell abutting the first memory cell, and the fourth transistor is a pull-down transistor of the second memory cell. 
     
     
         13 . The method of  claim 11 , wherein after the forming of the gate via, either of the third and fourth transistors is free of a gate via electrically coupled thereto. 
     
     
         14 . The method of  claim 11 , wherein the dielectric layer is deposited on a frontside of the semiconductor device, and the gate via opening exposes a top surface of the first gate. 
     
     
         15 . The method of  claim 11 , wherein the dielectric layer is deposited on a backside of the semiconductor device, and the gate via opening exposes a bottom surface of the first gate. 
     
     
         16 . The method of  claim 11 , wherein the gate via opening is a first gate via opening and the gate via is a first gate via, the method further comprising:
 forming a second gate via opening through the dielectric layer and exposing the first gate;   doping a threshold voltage tuning dopant into the first gate through the second gate via opening; and   forming a second gate via in the second gate via opening.   
     
     
         17 . The method of  claim 11 , wherein after the doping of the threshold voltage tuning dopant, a threshold voltage of the first and second transistors is higher than that of the third and fourth transistors. 
     
     
         18 . A memory device, comprising:
 a plurality of first nanostructures vertically stacked;   a plurality of second nanostructures vertically stacked and laterally spaced apart from the first nanostructures;   a gate structure wrapping around each of the first and second nanostructures;   a gate via electrically coupled to the gate structure; and   a threshold voltage tuning dopant distributed in a gate electrode layer of the gate structure, wherein a peak of a concentration of the threshold voltage tuning dopant is vertically aligned with the gate via.   
     
     
         19 . The memory device of  claim 18 , wherein the gate via is a first gate via, the memory device further comprising:
 a second gate via electrically coupled to the gate structure,   wherein the first gate via is disposed on a bottom surface of the gate structure, and the second gate via is disposed on a top surface of the gate structure.   
     
     
         20 . The memory device of  claim 18 , wherein the gate via is a first gate via, the memory device further comprising:
 a second gate via electrically coupled to the gate structure,   wherein the first and second gate vias are disposed on a same side of the gate structure, wherein the peak of the concentration of the threshold voltage tuning dopant is a first peak, and wherein a second peak of the concentration of the threshold voltage tuning dopant is vertically aligned with the second gate via.