Multi-gate device structure

Abstract

A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes first channel members between a first and a second source/drain feature, a first gate structure wrapping around the first channel members, a first source/drain contact disposed over the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact. The second transistor includes second channel members between a third and a fourth source/drain features, a second gate structure wrapping around the second channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact. A distance between the second gate spacer and the second source/drain contact is greater than a distance between the first gate spacer and the first source/drain contact.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first active region extending lengthwise along a first direction, wherein a channel region of the first active region comprises a plurality of nanostructures;   a first gate structure extending lengthwise along a second direction different from the first direction, wherein the first gate structure comprises a gate dielectric layer over the first active region and a gate electrode over the gate dielectric layer, wherein the gate electrode comprises a titanium-containing material;   a first dielectric feature disposed on a sidewall of the first gate structure;   a second gate structure extending lengthwise along the second direction and extending over the first active region;   a second dielectric feature disposed on a sidewall of the second gate structure;   a first source/drain contact disposed between the first dielectric feature and the second dielectric feature;   a second active region extending lengthwise along the first direction;   a third gate structure extending lengthwise along the second direction and extending over the second active region;   a fourth gate structure extending lengthwise along the second direction and extending over the second active region; and   a second source/drain contact disposed between the third gate structure and the fourth gate structure,   wherein, in a top view, a spacing between the first and second dielectric features is equal to a width of the first source/drain contact, and a spacing between the third and fourth gate structures is greater than a width of the second source/drain contact.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first active region comprises a first source/drain feature under the first source/drain contact, the second active region comprises a second source/drain feature under the second source/drain contact, and wherein a top surface of the first source/drain feature is above a top surface of the second source/drain feature. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a gate pitch of the first and second gate structures is less than a gate pitch of the third and fourth gate structures. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a third dielectric feature disposed on a sidewall of the third gate structure,   wherein the first dielectric feature has a first thickness along the first direction, the third dielectric feature has a second thickness along the first direction, the second thickness is greater than the first thickness.   
     
     
         5 . The semiconductor device of  claim 1 , wherein the width of the second source/drain contact is greater than the width of the first source/drain contact. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 an isolation structure disposed adjacent to an end portion of the first gate structure along the second direction.   
     
     
         7 . The semiconductor device of  claim 6 , wherein a top surface of the isolation structure is above a top surface of the first gate structure. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising:
 a dielectric cap extending on a top surface of the first gate structure, and   a dielectric layer disposed between the third gate structure and the second source/drain contact, wherein the dielectric cap and the dielectric layer have different compositions.   
     
     
         9 . The semiconductor device of  claim 1 , wherein the first source/drain contact is disposed adjacent to a first side of the first gate structure, the semiconductor device further comprises a third source/drain contact disposed adjacent to a second side of the first gate structure, the second side is different from the first side, and a length of the third source/drain contact along the second direction is different from a length of the first source/drain contact along the second direction. 
     
     
         10 . A semiconductor device, comprising:
 a device region comprising:
 a first active region comprising a first channel region, a second channel region, and a source/drain feature disposed between the first channel region and the second channel region, wherein the first channel region comprises a plurality of nanostructures, 
 a second active region adjacent to the first active region, 
 a first gate structure wrapping around the plurality of nanostructures, 
 a second gate structure disposed over the second channel region, wherein the source/drain feature is disposed between the first gate structure and the second gate structure, and the second gate structure is spaced apart from the first gate structure by a first spacing, 
 a gate spacer disposed along a sidewall of the first gate structure, wherein the first gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer, wherein a dielectric constant of the gate dielectric layer is greater than a dielectric contact of the gate spacer, 
 a silicide layer on the source/drain feature, and 
 a source/drain contact on the silicide layer, wherein an electrical conductivity of the silicide layer is between an electrical conductivity of the source/drain feature and an electrical conductivity of the source/drain contact, and wherein when viewed from top, the source/drain contact straddles the first active region and the second active region; and 
   a second device region comprising two adjacent gate structures separated from each other by a second spacing, wherein the second spacing is different from the first spacing.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the first channel region comprises a plurality of nanostructures. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the device region further comprises:
 a plurality of inner spacers disposed between the first gate structure and the source/drain feature, wherein the gate spacer is spaced apart from a topmost inner spacer feature of the plurality of inner spacers.   
     
     
         13 . The semiconductor device of  claim 11 ,
 wherein the device region comprises a first dielectric cap over top surfaces of the first gate structure and the gate spacer, and   wherein the second device region comprises a second dielectric cap over one of the two adjacent gate structures in the second device region.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the source/drain contact extends along a sidewall surface of the first dielectric cap. 
     
     
         15 . The semiconductor device of  claim 13 , further comprising:
 a dielectric layer disposed between the two adjacent gate structures in the second device region,   wherein there is an etch selectivity between the dielectric layer and the first and second dielectric caps.   
     
     
         16 . The semiconductor device of  claim 10 , further comprising:
 another device region comprising two adjacent gate structures separated from each other by a second spacing, wherein the second spacing is different from the first spacing.   
     
     
         17 . A semiconductor device, comprising:
 a first device region comprising:
 a first active region comprising a first channel region, a second channel region, and a first source/drain region disposed between the first channel region and the second channel region, wherein the first channel region comprises a plurality of nanostructures, 
 a first gate structure over the first channel region and wrapping around the plurality of nanostructures, 
 a first dielectric cap over the first gate structure, 
 a second gate structure over the second channel region, 
 a second dielectric cap over the second gate structure, 
 a first source/drain feature over the first source/drain region, and 
 a first source/drain contact electrically coupled to the first source/drain feature and disposed between the first dielectric cap and the second dielectric cap, wherein an electrical conductivity of the first source/drain contact is greater than an electrical conductivity of the first source/drain feature; and 
   a second device region comprising:
 a second active region comprising a third channel region, a fourth channel region, and a second source/drain region disposed between the third channel region and the fourth channel region; 
 a third gate structure over the third channel region; 
 a third dielectric cap over the third gate structure, 
 a fourth gate structure over the fourth channel region; 
 a fourth dielectric cap over the fourth gate structure, 
 a second source/drain feature over the second source/drain region; 
 a dielectric layer extending along a sidewall of the third gate structure, a sidewall of the third dielectric cap, a top surface of the second source/drain feature, a sidewall of the fourth gate structure, and a sidewall of the fourth dielectric cap, wherein a composition of the dielectric layer is different from a composition of the third dielectric cap and the fourth dielectric cap, 
   wherein a spacing between the first gate structure and the second gate structure is different from a spacing between the third gate structure and the fourth gate structure.   
     
     
         18 . The semiconductor device of  claim 17 , wherein the first device region further comprises:
 a first gate spacer extending along a sidewall surface of the first gate structure, and   a second gate spacer extending along a sidewall surface of the second gate structure,   wherein the first dielectric cap further extends on the first gate spacer, and the second dielectric cap further extends on the second gate spacer.   
     
     
         19 . The semiconductor device of  claim 17 , wherein the first source/drain contact interfaces with the first dielectric cap and the second dielectric cap. 
     
     
         20 . The semiconductor device of  claim 17 , wherein, the second device region further comprises a second source/drain contact over the second source/drain feature, and viewed from top, a width of the first source/drain contact is less than a width of the second source/drain contact.