Semiconductor package

Abstract

A semiconductor package may include a package substrate, a first interposer on the package substrate, a first semiconductor chip and a second semiconductor chip that are on the first interposer, a second interposer on the first semiconductor chip, a third semiconductor chip on the second interposer, and a first through via that extends into the first semiconductor chip and is between the first interposer and the second interposer.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a package substrate;   a first interposer on the package substrate;   a first semiconductor chip and a second semiconductor chip that are on the first interposer;   a second interposer on the first semiconductor chip;   a third semiconductor chip on the second interposer; and   a first through via that extends into the first semiconductor chip and is between the first interposer and the second interposer.   
     
     
         2 . The semiconductor package of  claim 1 , further comprising a plurality of third semiconductor chips that comprise the third semiconductor chip, wherein the plurality of third semiconductor chips are on the second interposer and are spaced apart from each other in a first direction that is parallel to an upper surface of the package substrate. 
     
     
         3 . The semiconductor package of  claim 2 , wherein:
 the second semiconductor chip is spaced apart from the first semiconductor chip in the first direction; and   the plurality of third semiconductor chips are spaced apart from the first semiconductor chip in a second direction that is perpendicular to the upper surface of the package substrate.   
     
     
         4 . The semiconductor package of  claim 2 , further comprising a plurality of first semiconductor chips that comprise the first semiconductor chip, wherein the plurality of first semiconductor chips are between the first interposer and the second interposer. 
     
     
         5 . The semiconductor package of  claim 4 , wherein each of the plurality of first semiconductor chips comprises a logic chip. 
     
     
         6 . The semiconductor package of  claim 5 , further comprising a plurality of through vias that comprise the first through via, wherein the plurality of through vias respectively extend into each of the plurality of first semiconductor chips. 
     
     
         7 . The semiconductor package of  claim 4 , wherein the plurality of first semiconductor chips comprises a logic chip and a dummy chip. 
     
     
         8 . The semiconductor package of  claim 7 , further comprising a second through via that extends into the dummy chip, wherein the first through via extends into the logic chip. 
     
     
         9 . The semiconductor package of  claim 7 , wherein the first through via only extends into the dummy chip. 
     
     
         10 . The semiconductor package of  claim 1 , wherein:
 the first semiconductor chip comprises a logic chip; and   the second semiconductor chip and the third semiconductor chip comprise memory chips.   
     
     
         11 . A semiconductor package, comprising:
 a package substrate;   a first interposer and a second interposer that are on an upper surface of the package substrate and are spaced apart from each other in a first direction that is perpendicular to an upper surface of the package substrate;   a first semiconductor chip that is between an upper surface of the first interposer and a lower surface of the second interposer;   a second semiconductor chip that is on the upper surface of the first interposer and is spaced apart from a side surface of the first semiconductor chip in a second direction that is parallel to the upper surface of the package substrate;   a plurality of third semiconductor chips that are on an upper surface of the second interposer and are spaced apart from each other in the second direction; and   a first through via that extends into the first semiconductor chip and is between the first interposer and the second interposer.   
     
     
         12 . The semiconductor package of  claim 11 , further comprising a plurality of first semiconductor chips that comprise the first semiconductor chip, wherein the plurality of first semiconductor chips are between the upper surface of the first interposer and the lower surface of the second interposer. 
     
     
         13 . The semiconductor package of  claim 12 , wherein:
 each of the plurality of first semiconductor chips comprises a logic chip.   
     
     
         14 . The semiconductor package of  claim 12 , further comprising a second through via, wherein:
 the plurality of first semiconductor chips comprises a dummy chip;   the first semiconductor chip of the plurality of first semiconductor chips comprises a logic chip; and   the second through via extends into the dummy chip.   
     
     
         15 . The semiconductor package of  claim 12 , wherein:
 the plurality of first semiconductor chips comprises a logic chip; and   the first semiconductor chip of the plurality of first semiconductor chips comprises a dummy chip.   
     
     
         16 . The semiconductor package of  claim 11 , wherein the first semiconductor chip is a logic chip, and the second semiconductor chip and the plurality of third semiconductor chips are memory chips. 
     
     
         17 . The semiconductor package of  claim 16 , wherein the second semiconductor chip comprises a plurality of memory chips that are stacked in the first direction. 
     
     
         18 . The semiconductor package of  claim 11 , wherein the first interposer comprises:
 a first interposer substrate;   a plurality of first interposer-through vias that extend into the first interposer substrate; and   a first wiring portion on the first interposer substrate,   wherein the first wiring portion and the plurality of first interposer-through vias connect the first semiconductor chip, the second semiconductor chip, and the package substrate to each other.   
     
     
         19 . The semiconductor package of  claim 18 , wherein the second interposer comprises:
 a second interposer substrate;   a plurality of second interposer-through vias that extend into the second interposer substrate; and   a second wiring portion on the second interposer substrate,   wherein the second wiring portion and the plurality of second interposer-through vias electrically connect the plurality of third semiconductor chips to the first semiconductor chip and/or electrically connect the plurality of third semiconductor chips to each other.   
     
     
         20 . A semiconductor package, comprising:
 a package substrate;   an external connection member on a lower surface of the package substrate;   a first interposer on an upper surface of the package substrate;   a first interposer connection member that is between an upper surface of the package substrate and a lower surface of the first interposer;   a first semiconductor chip and a second semiconductor chip that are on an upper surface of the first interposer and are spaced apart from each other in a first direction that is parallel to an upper surface of the package substrate;   a first connection member that is between the upper surface of the first interposer and a lower surface of the first semiconductor chip;   a second connection member that is between the upper surface of the first interposer and a lower surface of the second semiconductor chip;   a second interposer on an upper surface of the first semiconductor chip;   a second interposer connection member that is between an upper surface of the first semiconductor chip and a lower surface of the second interposer;   a plurality of third semiconductor chips that are on an upper surface of the second interposer and are spaced apart from each other in the first direction;   a third connection member that is between the upper surface of the second interposer and a lower surface of each of the plurality of third semiconductor chips;   a molding member on the upper surface of the first interposer, the first interposer connection member, the first semiconductor chip, the second semiconductor chip, the first connection member, the second connection member, the second interposer, the second interposer connection member, the plurality of third semiconductor chips, and the third connection member; and   a through via that extends into the first semiconductor chip and physically connects the first interposer and the second interposer.