Semiconductor device including overlay keys and method of manufacturing the same

Abstract

A semiconductor device including overlay keys and a method of manufacturing the device are provided. The semiconductor device includes first, second, third, and fourth pattern arrays. The first pattern array includes first conductive patterns and first overlay key segments. The second pattern array includes second overlay key segments and third overlay key segments. The third pattern array includes third conductive patterns and fourth overlay key segments. The fourth pattern array includes fifth overlay key segments and sixth overlay key segments. The first, second, third, fourth, fifth, and sixth overlay key segments provide alignment information of the fourth pattern array with respect to the first, second, and third pattern arrays.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first pattern array including first conductive patterns and first overlayer key segments formed over a semiconductor substrate;   a second pattern array including second conductive patterns, second overlay key segments, and third overlay key segments;   a third pattern array including third conductive patterns and fourth overlay key segments; and   a fourth pattern array including fourth conductive patterns, fifth overlay key segments, and sixth overlay key segments,   wherein the first, second, third, fourth, fifth, and sixth overlay key segments provide alignment of the fourth conductive patterns relative to the first, second, and third conductive patterns.   
     
     
         2 . The semiconductor device of  claim 1 ,
 wherein the first conductive patterns extend in a first direction and are spaced apart from each other along a second direction intersecting the first direction, and the first overlayer key segments are spaced apart from each other along the second direction,   wherein the second overlay key segments are spaced apart from each other along the first direction, and the third overlay key segments are spaced apart from each other along the second direction,   wherein the third conductive patterns extend in the second direction and are spaced apart from each other along the first direction, and the fourth overlay key segments are spaced apart from each other along the first direction, and   wherein each of the fourth conductive patterns is connected to the first, second, and third conductive patterns, and a portion of the semiconductor substrate, the fifth overlay key segments are spaced apart from each other along the first direction, and the sixth overlay key segments are spaced apart from each other along the second direction.   
     
     
         3 . The semiconductor device of  claim 2 ,
 wherein the semiconductor substrate includes a cell array region, a peripheral circuit region and an overlay key region,   wherein the first conductive patterns are located over the cell array region, and the second conductive patterns are located over the peripheral circuit region, and   wherein the first, second, third, fourth, fifth, and sixth overlay key segments are located over the overlay key region.   
     
     
         4 . The semiconductor device of  claim 3 ,
 wherein one of the second conductive patterns is spaced apart from the cell array region in the first direction, and   wherein another of the second conductive patterns is spaced apart from the cell array region in the second direction.   
     
     
         5 . The semiconductor device of  claim 1 , wherein the first conductive patterns and the first overlay key segments are positioned to be embedded in the semiconductor substrate. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the third conductive patterns cross over the first conductive patterns. 
     
     
         7 . The semiconductor device of  claim 1 ,
 wherein the first overlay key segments are formed at the same time as the first conductive patterns in the first pattern array,   wherein the second and third overlay key segments are formed at the same time as the second conductive patterns in the second pattern array,   wherein the fourth overlay key segments are formed at the same time as the third conductive patterns in the third pattern array, and   wherein the fifth and sixth overlay key segments are formed at the same time as the fourth conductive patterns in the fourth pattern array.   
     
     
         8 . The semiconductor device of  claim 1 , wherein the first overlay key segments have a bar feature. 
     
     
         9 . The semiconductor device of  claim 2 , wherein the fourth conductive patterns are spaced apart from each other along the first direction and the second direction. 
     
     
         10 . The semiconductor device of  claim 2 , further comprising a fifth pattern array including fifth conductive patterns, seventh overlay key segments, and eighth overlay key segment,
 wherein the fifth conductive patterns are connected to the fourth conductive patterns, the seventh overlay key segments are spaced apart from each other along the first direction, and the eighth overlay key segments are spaced apart from each other along the second direction.   
     
     
         11 . The semiconductor device of  claim 10 ,
 wherein some of the fifth conductive patterns extend in the first direction and are spaced apart from each other in the second direction, and   wherein other ones of the fifth conductive patterns extend in the second direction and are spaced apart from each other in the first direction.   
     
     
         12 . The semiconductor device of  claim 10 , wherein the fourth conductive pattern includes a connection contact, and
 wherein the connection contact connects the fifth conductive pattern to the first, second, third conductive patterns or a portion of the semiconductor substrate.   
     
     
         13 . The semiconductor device of  claim 1 ,
 wherein the first conductive patterns include word lines,   wherein the second conductive patterns include gate patterns of transistors,   wherein the third conductive patterns include bit lines, and   wherein the fourth conductive patterns include connection contacts connected to the word lines, the bit lines, and the transistors.   
     
     
         14 . A semiconductor device comprising:
 a first pattern array including first conductive patterns and first overlayer key segments formed over a semiconductor, the first conductive patterns extending in a first direction and spaced apart from each other along a second direction intersecting the first direction, and the first overlay key segments spaced apart from each other along the second direction;   a second pattern array including second conductive patterns, second overlay key segments and third overlay key segments, the second overlay key segments spaced apart from each other along the first direction, and the third overlay key segments spaced apart from each other along the second direction;   a third pattern array including third conductive patterns and fourth overlay key segments, the third conductive patterns extending in the second direction and spaced apart from each other along the first direction, and the fourth overlay key segments spaced apart from each other along the first direction;   a sixth pattern array including sixth conductive patterns, ninth overlay key segments, and tenth overlay key segments, the sixth conductive patterns passing between the third conductive patterns and connecting to some portions of the semiconductor substrate, the ninth overlay key segments spaced apart from each other along the first direction, and the tenth overlay key segments spaced apart from each other along the second direction; and   a fourth pattern array including fourth conductive patterns, fifth overlay key segments, and sixth overlay key segments, each of the fourth conductive patterns connected to the first, second, third, and sixth conductive patterns and a portion of the semiconductor substrate, the fifth overlay key segments spaced apart from each other along the first direction, and the sixth overlay key segments spaced apart from each other along the second direction,   wherein the first, second, third, fourth, fifth, sixth, ninth, and tenth overlay key segments provide alignment of the fourth conductive patterns relative to the first, second, third, and sixth conductive patterns.   
     
     
         15 . The semiconductor device of  claim 14 ,
 wherein the semiconductor substrate includes a cell array region, a peripheral circuit region, and an overlay key region,   wherein the first conductive patterns are located over the cell array region, the second conductive patterns are located over the peripheral circuit region, the third conductive patterns cross over the first conductive patterns, and the sixth conductive patterns are located over the cell array region, and   wherein the first, second, third, fourth, fifth, sixth, ninth, and tenth overlay key segments are located over the overlay key region.   
     
     
         16 . The semiconductor device of  claim 14 ,
 wherein one of the second conductive patterns is spaced apart from the cell array region in the first direction, and   wherein another of the second conductive patterns is spaced apart from the cell array region in the second direction.   
     
     
         17 . The semiconductor device of  claim 14 , wherein the first conductive patterns and the first overlay key segments are positioned to be embedded in the semiconductor substrate. 
     
     
         18 . The semiconductor device of  claim 14 ,
 wherein the first overlay key segments are formed at the same time as the first conductive patterns in the first pattern array,   wherein the second and third overlay key segments are formed at the same time as the second conductive patterns in the second pattern array,   wherein the fourth overlay key segments are formed at the same time as the third conductive patterns in the third pattern array,   wherein the fifth and sixth overlay key segments are formed at the same time as the fourth conductive patterns in the fourth pattern array, and   wherein the ninth and tenth overlay key segments are formed at the same time as the sixth conductive patterns in the sixth pattern array.   
     
     
         19 . The semiconductor device of  claim 14 , wherein the fourth conductive patterns are spaced apart from each other along the first direction and the second direction. 
     
     
         20 . A method of manufacturing a semiconductor device, the method comprising:
 forming a first pattern array over a semiconductor substrate, the first pattern array including first conductive patterns and first overlayer key segments;   forming a second pattern array including second conductive patterns, second overlay key segments and third overlay key segments;   forming a third pattern array including third conductive patterns and fourth overlay key segments; and   forming a fourth pattern array including fourth conductive patterns, fifth overlay key segments, and sixth overlay key segments,   wherein the first, second, third, fourth, fifth, and sixth overlay key segments provide alignment of the fourth conductive patterns relative to the first, second, and third conductive patterns.