Semiconductor device

Abstract

A semiconductor device includes a first memory bank, a second memory bank and a first write driver. The first memory bank is coupled to a plurality of first data lines, and configured to operate according to a first data signal. The second memory bank is configured to operate according to the first data signal. The first write driver is disposed between the first memory bank and the second memory bank, and configured to adjust a voltage level of one of the plurality of first data lines when the first memory bank is written according to the first data signal.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first logic circuit configured to generate a first data signal according to a second data signal;   a second logic circuit configured to generate a third data signal according to the second data signal;   a first switch configured to be turned on according to the first data signal, to adjust a voltage level of a first data line to a reference voltage level when a first memory cell coupled to the first data line is written according to the second data signal;   a second switch configured to be turned on according to the third data signal, to adjust a voltage level of a second data line to the reference voltage level when a second memory cell coupled to the second data line is written according to the second data signal; and   a third switch coupled in series with the first switch, and configured to provide a reference voltage signal having the reference voltage level to the first switch.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a fourth switch coupled in series with the third switch, configured to adjust a voltage level of a first complementary data line to the reference voltage level when the first memory cell is written according to the second data signal,   wherein a logic value of the first complementary data line and a logic value of the first data line are complementary with each other.   
     
     
         3 . The semiconductor device of  claim 2 , further comprising:
 a fifth switch, a control terminal of the fifth switch coupled to a control terminal of the first switch;   a sixth switch to the fifth switch, a control terminal of the sixth switch coupled to a control terminal of the fourth switch; and   a seventh switch coupled in series with each of the fifth switch and the sixth switch, and configure to receive the reference voltage signal.   
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a first memory bank disposed between the first switch and the second switch, and comprising the first memory cell.   
     
     
         5 . The semiconductor device of  claim 4 , wherein the second switch is disposed between the first memory bank and the second memory cell. 
     
     
         6 . A method, comprising:
 generating each of a first data signal and a second data signal according to a third data signal;   turning on a first switch by the first data signal;   providing a reference voltage signal to a first data line by the first switch when the a first memory cell coupled to the first data line is written according to the third data signal;   turning on a second switch by the second data signal;   providing the reference voltage signal to a second data line by the second switch when the a second memory cell coupled to the second data line is written according to the third data signal; and   providing the reference voltage signal to the first switch by a third switch coupled in series with the first switch.   
     
     
         7 . The method of  claim 6 , further comprising:
 providing the reference voltage signal to a first complementary data line by a fourth switch coupled in series with the third switch,   wherein a logic value carried by the first data line is complementary with a logic value carried by the first complementary data line.   
     
     
         8 . The method of  claim 6 , further comprising:
 turning on a fourth switch by the first data signal; and   providing the reference voltage signal to a third data line by the fourth switch when the a third memory cell coupled to the third data line is written according to the third data signal.   
     
     
         9 . The method of  claim 8 , further comprising:
 providing the reference voltage signal to the fourth switch by a fifth switch coupled in series with the fourth switch.   
     
     
         10 . The method of  claim 9 , further comprising:
 providing the reference voltage signal to the second switch by a fourth switch coupled in series with the second switch.   
     
     
         11 . The method of  claim 6 , further comprising:
 receiving the third data signal by a first inverter; and   outputting the first data signal by the first inverter.   
     
     
         12 . The method of  claim 11 , further comprising:
 generating a fourth data signal according to a fifth data signal;   turning on a fourth switch by the fourth data signal; and   providing the reference voltage signal to a first complementary data line by the fourth switch when the first memory cell is written according to the fifth data signal,   wherein the first memory cell is coupled to the first complementary data line.   
     
     
         13 . The method of  claim 12 , wherein a logic value carried by the first data line is complementary with a logic value carried by the first complementary data line, and
 a logic value of the first data signal is complementary with a logic value of the fourth data signal.   
     
     
         14 . The method of  claim 12 , further comprising:
 receiving the fifth data signal by a second inverter; and   outputting the fourth data signal by the second inverter.   
     
     
         15 . A semiconductor device, comprising:
 a first assisting circuit, comprising:
 a first switch configured to provide a reference voltage signal to a first data line according to a first data signal; 
 a second switch configured to provide the reference voltage signal to a first complementary data line according to a second data signal complementary with the first data signal; and 
 a third switch coupled in series with and configured to provide the reference voltage signal to each of the first switch and the second switch; and 
   a first logic element configured to generate the first data signal according to a first address signal; and   a second logic element configured to generate the second data signal according to the first address signal.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the first assisting circuit further comprises:
 a fourth switch configured to provide the reference voltage signal to a second data line according to the first data signal.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the first assisting circuit further comprises:
 a fifth switch coupled in series with and configured to provide the reference voltage signal to the fourth switch.   
     
     
         18 . The semiconductor device of  claim 17 , further comprising:
 a decoder configured to generate a first control signal and a second control signal according to a second address signal corresponding to the first data line,   wherein a control terminal of the third switch and a control terminal of the fifth switch are configured to receive the first control signal and the second control signal, respectively.   
     
     
         19 . The semiconductor device of  claim 18 , further comprising:
 a second assisting circuit configured to adjust a voltage level of a third data line according to the first control signal, the second control signal and a third data signal; and   a third logic element configured to receive a third address signal and output the third data signal.   
     
     
         20 . The semiconductor device of  claim 19 , further comprising:
 an inverter configured to receive the third address signal and output the first address signal.