Source/Drains for Stacked Device Structures and Methods of Fabrication Thereof

Abstract

Source/drain fabrication methods for stacked device structures are disclosed herein. An exemplary method for forming a source/drain stack may include a frontside process and a backside process. The frontside process may include forming a frontside source/drain trench, forming a dummy source/drain in the frontside source/drain trench, and forming an upper source/drain in the frontside source/drain trench over the dummy source/drain. The backside process may include exposing a backside of the dummy source/drain, removing (partially or completely) the dummy source/drain to form a backside source/drain trench, and forming a lower source/drain in the backside source/drain trench. The dummy source/drain may be formed of semiconductor material or dielectric material, and a portion of the dummy source/drain may remain between the upper source/drain and the lower source/drain. In some embodiments, the backside process includes replacing substrate/mesa with a backside insulation structure and selectively removing the dummy source/drain relative to the backside insulation structure.

What is claimed is: 
     
         1 . A method comprising:
 forming a first source/drain trench having a first aspect ratio;   filling a first portion of the first source/drain trench with a sacrificial source/drain, wherein the sacrificial source/drain is formed of an insulation material and the first portion of the first source/drain trench corresponds with a first device;   filling a second portion of the first source/drain trench with a first source/drain, wherein the first source/drain is formed of a first semiconductor material and the second portion of the first source/drain trench corresponds with a second device;   after filling the second portion of the first source/drain trench with the first source/drain, at least partially removing the sacrificial source/drain to form a second source/drain trench having a second aspect ratio less than the first aspect ratio; and   filling a portion of the second source/drain trench with a second source/drain, wherein the second source/drain is formed of a second semiconductor material and the portion of the second source/drain trench corresponds with the first device.   
     
     
         2 . The method of  claim 1 , wherein filling the first portion of the first source/drain trench with the sacrificial source/drain includes:
 depositing a dielectric material in the first source/drain trench; and   etching back the dielectric material, such that the dielectric material is removed from the second portion of the first source/drain trench that corresponds with the second device.   
     
     
         3 . The method of  claim 2 , wherein:
 the depositing the dielectric material includes performing a blanket deposition process, such that the dielectric material is deposited inside and outside the first source/drain trench; and   a portion of the dielectric material remains outside the first source/drain trench after the etching back of the dielectric material.   
     
     
         4 . The method of  claim 2 , wherein:
 the depositing the dielectric material includes performing a spin-on deposition process, such that the dielectric material is deposited inside and outside the first source/drain trench; and   a portion of the dielectric material remains outside the first source/drain trench after the etching back of the dielectric material.   
     
     
         5 . The method of  claim 1 , further comprising:
 before filling the second portion of the first source/drain trench with the first source/drain, filling a third portion of the first source/drain trench with a source/drain isolation structure, wherein the third portion of the first source/drain trench is disposed between the first portion of the first source/drain trench and the second portion of the first source/drain trench and the third portion of the first source/drain trench corresponds with a device isolation region between the first device and the second device; and   completely removing the sacrificial source/drain to form the second source/drain trench.   
     
     
         6 . The method of  claim 5 , wherein the filling the third portion of the first source/drain trench with the source/drain isolation structure includes:
 forming a contact etch stop layer over the sacrificial source/drain, wherein the contact etch stop layer is formed inside and outside the first source/drain trench; and   forming an interlayer dielectric layer over the contact etch stop layer, wherein the interlayer dielectric layer is formed inside and outside the first source/drain trench.   
     
     
         7 . The method of  claim 1 , further comprising:
 filling a third portion of the first source/drain trench with the sacrificial source/drain, wherein the third portion of the first source/drain trench is disposed between the first portion of the first source/drain trench and the second portion of the first source/drain trench and the third portion of the first source/drain trench corresponds with a device isolation region between the first device and the second device; and   partially removing the sacrificial source/drain to form the second source/drain trench, wherein a remainder of the sacrificial source/drain provides a source/drain isolation structure between the first source/drain and the second source/drain.   
     
     
         8 . The method of  claim 1 , wherein the filling the portion of the second source/drain trench with the second source/drain includes epitaxially growing the second semiconductor material and implementing an epitaxial growth temperature that is less than about 400° C. 
     
     
         9 . The method of  claim 1 , wherein:
 the first aspect ratio is at least 10;   the second aspect ratio is at least 1; and   the second aspect ratio is less than 10.   
     
     
         10 . The method of  claim 9 , wherein:
 a first width of the first source/drain trench is less than about 20 nm; and   a second width of the second source/drain trench is less than about 20 nm.   
     
     
         11 . A method comprising:
 forming a source/drain trench that extends through an upper multilayer stack, a lower multilayer stack, an intermediate stack between the upper multilayer stack and the lower multilayer stack, and into a semiconductor substrate;   depositing a dielectric material in the source/drain trench and etching back the dielectric material to form a dielectric layer in a portion of the source/drain trench disposed in the lower multilayer stack and in the semiconductor substrate;   forming a first type source/drain over the dielectric layer in a portion of the source/drain trench disposed in the upper multilayer stack;   after removing a portion of the semiconductor substrate to expose the dielectric layer, replacing at least a portion of the dielectric layer with a second type source/drain; and   before replacing at least the portion of the dielectric layer with the second type source/drain, replacing a portion of the upper multilayer stack with a first gate stack and a portion of the lower multilayer stack with a second gate stack.   
     
     
         12 . The method of  claim 11 , wherein the source/drain trench is a first source/drain trench, the method further comprising:
 after removing the portion of the semiconductor substrate to expose the dielectric layer, replacing the semiconductor substrate with an insulation structure; and   wherein the replacing at least the portion of the dielectric layer with the second type source/drain includes:
 selectively removing the dielectric layer with respect to the insulation structure, semiconductor layers of the lower multilayer stack, and inner spacers of the lower multilayer stack to form a second source/drain trench, and 
 epitaxially growing a semiconductor material in the second source/drain trench using a temperature less than about 400° C. 
   
     
     
         13 . The method of  claim 12 , wherein the semiconductor material partially fills the second source/drain trench, the method further comprising filling a remainder of the second source/drain trench with a contact etch stop layer and an interlayer dielectric layer. 
     
     
         14 . The method of  claim 12 , wherein the selectively removing the dielectric layer to form the second source/drain trench completely removes the dielectric layer from a source/drain region to expose a source/drain isolation structure, wherein the source/drain isolation structure remains between the first type source/drain and the second type source/drain. 
     
     
         15 . The method of  claim 12 , wherein the selectively removing the dielectric layer to form the second source/drain trench partially removes the dielectric layer from a source/drain region, wherein a remainder of the dielectric layer in the source/drain region remains disposed between the first type source/drain and the second type source/drain. 
     
     
         16 . The method of  claim 11 , wherein the dielectric material is formed of a silicon-comprising material that includes oxygen, carbon, nitrogen, or combinations thereof. 
     
     
         17 . The method of  claim 11 , wherein the dielectric material is formed of a boron-comprising material that includes oxygen, carbon, nitrogen, or combinations thereof. 
     
     
         18 . A device structure comprising:
 a source/drain stack that includes a first source/drain, a second source/drain disposed over the first source/drain, and a source/drain isolation structure disposed between the second source/drain and the first source/drain, wherein the first source/drain is formed of a first semiconductor material, the second source/drain is formed of a second semiconductor material, and the second semiconductor material is different from the first semiconductor material;   a contact etch stop layer and an interlayer dielectric layer disposed over the second source/drain, wherein the contact etch stop layer is disposed between sidewalls of the second source/drain and the interlayer dielectric layer; and   a dummy source/drain layer disposed between the contact etch stop layer and a substrate isolation structure, wherein the dummy source/drain layer is formed of an insulation material and the dummy source/drain layer is disposed along sidewalls of the first source/drain.   
     
     
         19 . The device structure of  claim 18 , wherein the source/drain isolation structure is formed from the dummy source/drain layer. 
     
     
         20 . The device structure of  claim 18 , wherein the contact etch stop layer is a first contact etch stop layer, the interlayer dielectric layer is a first interlayer dielectric layer, and the source/drain isolation structure is formed from a second contact etch stop layer and a second interlayer dielectric layer, wherein the second contact etch stop layer is disposed between the dummy source/drain layer and the second interlayer dielectric layer.