Storage device having latching units serially connected for in-memory arithmetic operations

Abstract

A method includes setting each latching unit in an array of latching units to a forward-connection mode for a duration of a first time period while each inter-unit transmission switch in a plurality of inter-unit transmission switches is at a connected state, and after the first time period, setting each latching unit in the array of latching units to a latch mode and setting each inter-unit transmission switch to a disconnected state. The method also includes setting each latching unit in the array of latching units to a backward-connection mode for a duration of a second time period while each inter-unit transmission switch is at a connected state, and after the second time period, setting each latching unit in the array of latching units to a latch mode and setting each inter-unit transmission switch to a disconnected state.

What is claimed is: 
     
         1 . A method of comprising:
 setting each latching unit in an array of latching units to a forward-connection mode for a duration of a first time period while each inter-unit transmission switch in a plurality of inter-unit transmission switches is at a connected state, wherein each latching unit having a first bit node and a second bit node, wherein the array of latching units includes a first latching unit, a last latching unit, and remaining latching units serially coupled between the first latching unit and the last latching unit;   after the first time period, setting each latching unit in the array of latching units to a latch mode and setting each inter-unit transmission switch to a disconnected state;   setting each latching unit in the array of latching units to a backward-connection mode for a duration of a second time period while each inter-unit transmission switch is at a connected state; and   after the second time period, setting each latching unit in the array of latching units to a latch mode and setting each inter-unit transmission switch to a disconnected state.   
     
     
         2 . The method of  claim 1 , each latching unit having a first bit node and a second bit node, wherein a latching unit comprises:
 a first inverter and a first transmission switch serially connected between the first bit node and the second bit node, the first inverter having an input coupled to the first bit node either directly or through the first transmission switch; and   a second inverter and a second transmission switch serially connected between the second bit node and the first bit node, the second inverter having an input coupled to the second bit node either directly or through the second transmission switch.   
     
     
         3 . The method of  claim 2 , wherein setting each latching unit in the array of latching units to the forward-connection mode comprises:
 setting the first transmission switch in each latching unit to a connected state; and   setting the second transmission switch in each latching unit to a disconnected state.   
     
     
         4 . The method of  claim 2 , wherein setting each latching unit in the array of latching units the backward-connection mode comprises:
 setting the first transmission switch in each latching unit to a disconnected state; and   setting the second transmission switch in each latching unit to a connected state.   
     
     
         5 . The method of  claim 2 , wherein setting each latching unit in the array of latching units to the latch mode comprises:
 setting the first transmission switch in each latching unit to a disconnected state; and   setting the second transmission switch in each latching unit to a disconnected state.   
     
     
         6 . The method of  claim 1 , wherein each pair of two adjacent latching units is coupled together through an inter-unit transmission switch. 
     
     
         7 . The method of  claim 1 , the method comprising:
 applying a first voltage to the first bit node of the first latching unit and setting the second bit node of the last latching unit at floating during the first time period.   
     
     
         8 . The method of  claim 1 , the method comprising:
 applying a second voltage to the second bit node of the last latching unit and setting the first bit node of the first latching unit at floating during the second time period.   
     
     
         9 . The method of  claim 1 , further comprising:
 during the first time period, driving a PMOS transistor into a conducting state with a voltage applied to a gate thereof and driving an NMOS transistor into a non-conducting state with a voltage applied to a gate thereof, wherein the PMOS transistor has a drain thereof connected to the first bit node of the first latching unit and has a source thereof connected to an upper supply voltage, and wherein the PMOS transistor has a drain thereof connected to the second bit node of the last latching unit and has a source thereof connected to a lower supply voltage.   
     
     
         10 . The method of  claim 1 , further comprising:
 during the second time period, driving a PMOS transistor into a non-conducting state with a voltage applied to a gate thereof and driving an NMOS transistor into a conducting state with a voltage applied to a gate thereof, wherein the PMOS transistor has a drain thereof connected to the first bit node of the first latching unit and has a source thereof connected to an upper supply voltage, and wherein the PMOS transistor has a drain thereof connected to the second bit node of the last latching unit and has a source thereof connected to a lower supply voltage.   
     
     
         11 . A storage device comprising:
 an array of latching units including a first latching unit, a second latching unit, and a third latching unit, where in each latching unit comprises:
 a first inverter and a first transmission switch serially connected between a first bit node and a second bit node, the first inverter having an input configured to receive a voltage from the first bit node either directly or through the first transmission switch, 
 a second inverter and a second transmission switch serially connected between the second bit node and the first bit node, the second inverter having an input configured to receive a voltage from the second bit node either directly or through the second transmission switch; 
   a first inter-unit transmission switch electrically coupled between the second bit node of the first latching unit and the first bit node of the second latching unit; and   a second inter-unit transmission switch electrically coupled between the second bit node of the second latching unit and the first bit node of the third latching unit.   
     
     
         12 . The storage device of  claim 11 , wherein the first inverter is coupled between the first bit node and the first transmission switch, and the first transmission switch is coupled between an output of the first inverter and the second bit node. 
     
     
         13 . The storage device of  claim 11 , wherein the first transmission switch is coupled between the first bit node and the input of the first inverter, and the first inverter is coupled between the first transmission switch and the second bit node. 
     
     
         14 . The storage device of  claim 11 , wherein the second inverter is coupled between the second bit node and the second transmission switch, and the second transmission switch is coupled between an output of the second inverter and the first bit node. 
     
     
         15 . The storage device of  claim 11 , wherein the second transmission switch is coupled between the second bit node and the input of the second inverter, and the second inverter is coupled between the second transmission switch and the first bit node. 
     
     
         16 . A method of operating a storage device, the storage device comprising an array of latching units and a plurality of inter-unit transmission switches, each latching unit having a first bit node and a second bit node, the method comprising:
 performing a long pulse operation of forward-shifting on the storage device, wherein performing the long pulse operation of forward-shifting comprises:
 setting each latching unit in the array of latching units to a forward-connection mode for a duration of a long pulse while each inter-unit transmission switch is at a connected state and a first voltage is applied to the first bit node of a first latching unit; and 
   performing a short pulse operation of backward-shifting on the storage device, wherein performing the short pulse operation of backward-shifting comprises:
 setting each latching unit in the array of latching units to a backward-connection mode for a duration of a short pulse while each inter-unit transmission switch is at a connected state and a second voltage is applied to the second bit node of a last latching unit, and 
 after the short pulse, setting each latching unit in the array of latching units to a latch mode and setting each inter-unit transmission switch to a disconnected state. 
   
     
     
         17 . The method of  claim 16 , wherein performing the long pulse operation of forward-shifting further comprises:
 after the long pulse, setting each latching unit in the array of latching units to the latch mode and setting each inter-unit transmission switch to a disconnected state.   
     
     
         18 . The method of  claim 16 , wherein performing the long pulse operation of forward-shifting further comprises:
 setting the second bit node of the last latching unit at floating during the long pulse; and   causing a voltage at the second bit node of the last latching unit be settled to a level which is determined by the first voltage applied to the first bit node of the first latching unit.   
     
     
         19 . The method of  claim 16 , wherein performing the short pulse operation of backward-shifting comprises:
 causing a voltage at the first bit node of a given latching unit at an end of the short pulse operation be settled to a level which is determined by an initial voltage at the second bit node of the given latching unit at a beginning of the short pulse operation.   
     
     
         20 . The method of  claim 16 , comprising:
 detecting a voltage level at the first bit node of the first latching unit; and   performing another long pulse operation on the storage device in response to a voltage at the first bit node of the first latching unit is changed to a voltage that is different from the first voltage.