Integrated circuit device and method

Abstract

An integrated circuit (IC) device includes a complementary field-effect transistor (CFET) device, a first conductor at a first side of the CFET device, and a second conductor at a second side of the CFET device. The second side is opposite the first side along a thickness direction of the CFET device. The CFET device includes a local interconnect electrically coupling the first conductor to the second conductor, and a gate arranged in a plane that intersects the local interconnect. The gate is electrically isolated from the local interconnect.

What is claimed is: 
     
         1 . An integrated circuit (IC) device, comprising:
 a complementary field-effect transistor (CFET) device;   a first conductor at a first side of the CFET device; and   a second conductor at a second side of the CFET device, the second side opposite the first side along a thickness direction of the CFET device,   wherein the CFET device comprises:
 a local interconnect electrically coupling the first conductor to the second conductor, and 
 a gate arranged in a plane that intersects the local interconnect, the gate electrically isolated from the local interconnect. 
   
     
     
         2 . The IC device of  claim 1 , further comprising:
 a first via between and electrically coupling the local interconnect to the first conductor; and   a second via between and electrically coupling the local interconnect to the second conductor.   
     
     
         3 . The IC device of  claim 2 , further comprising:
 a contact structure between and electrically coupling the local interconnect to the second via.   
     
     
         4 . The IC device of  claim 1 , wherein
 the first conductor, the second conductor and the local interconnect are all elongated along a first direction.   
     
     
         5 . The IC device of  claim 1 , further comprising:
 a first dielectric material surrounding the local interconnect and electrically isolating the local interconnect from the gate of the CFET device.   
     
     
         6 . The IC device of  claim 5 , further comprising:
 a second dielectric material between the first dielectric material and the local interconnect,   wherein the second dielectric material has a lower dielectric constant than the first dielectric material.   
     
     
         7 . The IC device of  claim 1 , further comprising:
 a front side metal layer at the first side which is a front side of the CFET device, the front side metal layer comprising a plurality of front side conductive patterns elongated along a first direction,   wherein   the plurality of front side conductive patterns comprises:
 the first conductor, and 
 a first front side conductive pattern immediately adjacent to the first conductor in a second direction transverse to the first direction, and 
   the first front side conductive pattern overlaps the gate in the thickness direction transverse to both the first direction and the second direction.   
     
     
         8 . The IC device of  claim 7 , wherein
 the CFET device further comprises active regions elongated along the first direction,   the plurality of front side conductive patterns further comprises a second front side conductive pattern immediately adjacent to the first front side conductive pattern in the second direction, and   the second front side conductive pattern overlaps the gate and the active regions of the CFET device in the thickness direction.   
     
     
         9 . The IC device of  claim 8 , further comprising:
 a back side metal layer at the second side which is a back side of the CFET device, the back side metal layer comprising a plurality of back side conductive patterns elongated along the first direction,   wherein   the plurality of back side conductive patterns comprises:
 the second conductor, and 
 a first back side conductive pattern immediately adjacent to the second conductor in the second direction, and 
   the first back side conductive pattern overlaps the gate in the thickness direction.   
     
     
         10 . The IC device of  claim 9 , wherein
 the plurality of back side conductive patterns further comprises a second back side conductive pattern immediately adjacent to the first back side conductive pattern in the second direction, and   the second back side conductive pattern overlaps the gate and the active regions of the CFET device in the thickness direction.   
     
     
         11 . An integrated circuit (IC) device, comprising:
 a complementary field-effect transistor (CFET) device;   a front side metal layer comprising first to third front side conductive patterns over the CFET device, wherein
 the second front side conductive pattern is between the first and third front side conductive patterns, and 
 the first front side conductive pattern is wider than the second and third front side conductive patterns, 
   a back side metal layer comprising first to third back side conductive patterns under the CFET device, wherein
 the second back side conductive pattern is between the first and third back side conductive patterns, 
 the third back side conductive pattern is wider than the first and second back side conductive patterns, and 
 the first to third front side conductive patterns correspondingly overlaps the first to third back side conductive patterns; and 
   a local interconnect extending between and electrically coupling the first front side conductive pattern and the first back side conductive pattern.   
     
     
         12 . The IC device of  claim 11 , wherein
 the CFET device is a dummy CFET device.   
     
     
         13 . The IC device of  claim 11 , wherein
 the CFET device comprises at least one of
 floating source/drains and a floating gate, 
 one or more dummy source/drains comprising no epitaxy structure, or 
 a dummy gate comprising a dielectric material. 
   
     
     
         14 . The IC device of  claim 11 , wherein
 the CFET device comprises stacked active regions which overlap the third front side conductive pattern and the third back side conductive pattern.   
     
     
         15 . The IC device of  claim 11 , wherein
 the CFET device comprises stacked gates which overlap the second and third front side conductive patterns and the second and third back side conductive patterns, without overlapping the first front side conductive pattern and the first back side conductive pattern.   
     
     
         16 . A method, comprising:
 forming a plurality of complementary field-effect transistor (CFET) devices at a front side of a substrate;   forming a local interconnect within a cut-gate region, the cut-gate region resulting in a gate of a first CFET device among the plurality of CFET devices being shorter than a gate of a second CFET device among the plurality of CFET devices, the gate of the second CFET device immediately adjacent to the gate of the first CFET device;   depositing and patterning a front side redistribution structure; and   depositing and patterning a back side redistribution structure;   wherein   one of the front side redistribution structure and the back side redistribution structure comprises a power rail electrically coupled to one end of the local interconnect, and   the other of the front side redistribution structure and the back side redistribution structure comprises a conductor electrically coupled to another end of the local interconnect.   
     
     
         17 . The method of  claim 16 , wherein
 the conductor is a further power rail within the other of the front side redistribution structure and the back side redistribution structure.   
     
     
         18 . The method of  claim 16 , wherein
 said forming the local interconnect comprises embedding the local interconnect within a dielectric material corresponding to the cut-gate region, and   the dielectric material electrically isolating the local interconnect from the gate of the first CFET device.   
     
     
         19 . The method of  claim 16 , wherein
 said forming the local interconnect comprises embedding the local interconnect within a first dielectric material which is embedded within a second dielectric material corresponding to the cut-gate region, and   the first dielectric material has a lower dielectric constant than the second dielectric material.   
     
     
         20 . The method of  claim 16 , wherein
 at least one of said forming the plurality of CFET devices, said forming the front side redistribution structure or said forming the back side redistribution structure is performed to configure the first CFET device as a dummy CFET device.