Channel optimization for nanosheet technology

Abstract

A method of method of fabricating a semiconductor device includes providing a semiconductor structure having a sheet of vertically stacked formations including alternating semiconductor layers and sacrificial layers, surrounded by a layer of dummy gate material. The sacrificial layers are removed from the sheet leaving empty channels between the semiconductor layers. A gate oxide is deposited in the empty channels. The gate oxide wraps around the semiconductor layers in the sheet and defines layers of gate oxide. The layers of gate oxide are etched inward from a space between the vertically stacked formations, forming pockets between the layers of semiconductor. A dielectric spacer is deposited into the pockets. A source and drain formation is deposited into the space between the vertically stacked formations. The layer of dummy gate material is removed. The layers of gate oxide are removed. A gate is formed in contact with the semiconductor layers.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a source and drain on top of the substrate, wherein the source and drain comprise a doped silicon germanium epitaxy;   a plurality of vertically stacked semiconductor channels positioned adjacent the source and drain; and   a plurality of silicon dioxide layers positioned between the vertically stacked semiconductor channels.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a plurality of dielectric spacers between the source and drain and respective silicon dioxide layers. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the plurality of silicon dioxide layers wrap around the vertically stacked semiconductor channels. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a boron doped silicon germanium epitaxy is diffused into the vertically stacked semiconductor channels. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the diffusion of doped silicon germanium epitaxy into the vertically stacked semiconductor channels is partially above and below the plurality of silicon dioxide layers. 
     
     
         6 . The semiconductor device of  claim 1 , wherein a thickness of the silicon dioxide layers is between 6 to 10 nanometers. 
     
     
         7 . A method of fabricating a semiconductor device, comprising:
 providing a semiconductor structure having a plurality of vertically stacked formations including alternating semiconductor layers and sacrificial layers, surrounded by a layer of dummy gate material;   removing the sacrificial layers from the vertically stacked formations and leaving empty channels between the semiconductor layers;   depositing layers of a gate oxide in the empty channels, wherein each layer of the gate oxide wraps around the semiconductor layers;   etching the layers of gate oxide inward from a space between the vertically stacked formations, forming pockets between the semiconductor layers;   depositing a dielectric spacer into the pockets;   depositing a source and drain formation into the space between the vertically stacked formations;   removing the layer of dummy gate material;   removing the layers of gate oxide; and   forming a gate in contact with the semiconductor layers.   
     
     
         8 . The method of  claim 7 , wherein a material for the source and drain is deposited wrapped around the dielectric spacer deposited into the pockets. 
     
     
         9 . The method of  claim 8 , wherein the material for the source and drain is a boron doped silicon germanium epitaxy. 
     
     
         10 . The method of  claim 7 , wherein the layers of gate oxide are silicon dioxide. 
     
     
         11 . The method of  claim 7 , further comprising reducing a thickness of at least one semiconductor layer after removing the layers of gate oxide and prior to forming the gate. 
     
     
         12 . The method of  claim 11 , wherein the thickness of the at least one semiconductor layer is reduced up to the dielectric spacer deposited into the pockets and the at least one semiconductor layer has sections of different thicknesses. 
     
     
         13 . The method of  claim 7 , wherein a thickness of the sacrificial layers is between 6 to 10 nanometers. 
     
     
         14 . The method of  claim 7 , wherein the gate wraps around the semiconductor layers. 
     
     
         15 . The method of  claim 7 , further comprising forming a shallow trench isolation feature in between adjacent vertically stacked formations. 
     
     
         16 . A method of controlling a flow of dopants into channels of a semiconductor device, comprising:
 providing a semiconductor structure having a sheet of a plurality of vertically stacked formations including a plurality of semiconductor channels and sacrificial material wrapped around the semiconductor channels;   removing the sacrificial material from the sheet and leaving empty channels between the semiconductor channels;   depositing layers of a gate oxide into the empty channels, wherein the gate oxide wraps around the semiconductor channels in the sheet; and   depositing a source and drain epitaxy into a space between the vertically stacked formations, wherein the source and drain epitaxy includes a dopant and a rate of diffusion of the dopant into the semiconductor channels is slowed by a presence of the gate oxide.   
     
     
         17 . The method of  claim 16 , further comprising:
 etching the layers of gate oxide inward from a space between the vertically stacked formations, forming pockets between the plurality of semiconductor channels; and   depositing a dielectric spacer into the pockets.   
     
     
         18 . The method of  claim 17 , wherein the source and drain epitaxy is deposited wrapped around the dielectric spacer deposited into the pockets. 
     
     
         19 . The method of  claim 16 , wherein a material for the source and drain epitaxy is silicon germanium epitaxy and the dopant is boron. 
     
     
         20 . The method of  claim 19 , wherein the gate oxide is silicon dioxide.