Gate-all-around high-density and high-speed sram cells

Abstract

A semiconductor device includes a first cell and a second cell. The first cell includes first, second, and third transistors. Gate structures of the second and third transistors are coupled to each other. The first transistor has a first channel width, the second transistor has a second channel width, and the third transistor has a third channel width. The second channel width is greater than the first channel width. The second cell includes fourth, fifth, and sixth transistors. Gate structures of the fifth and sixth transistors are coupled to each other. The fourth transistor has a fourth channel width, the fifth transistor has a fifth channel width, the sixth transistor has a sixth channel width. The fourth channel width is equal to the fifth channel width. The fifth channel width is greater than the second channel width. The sixth channel width is greater than the third channel width.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first cell including first, second, and third transistors, gate structures of the second and third transistors coupled to each other, the first transistor having a first channel width, the second transistor having a second channel width, the third transistor having a third channel width, the second channel width being greater than the first channel width; and   a second cell including fourth, fifth, and sixth transistors, gate structures of the fifth and sixth transistors coupled to each other, the fourth transistor having a fourth channel width, the fifth transistor having a fifth channel width, the sixth transistor having a sixth channel width, the fourth channel width equal to the fifth channel width,   wherein the gate structures of the second, third, fifth, and sixth transistors comprise a gate dielectric layer and a gate electrode over the gate dielectric layer, the gate electrode comprises a titanium-containing material, and a thickness of the gate dielectric layer is less than a thickness of gate spacers disposed on sidewalls of the gate structures,   wherein the fifth channel width is greater than the second channel width, and the sixth channel width is greater than the third channel width.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first cell is a first SRAM cell in a first region of the semiconductor device, and the second cell is a second SRAM cell in a second region of the semiconductor device. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the first transistor is a pass-gate transistor, the second transistor is a pull-down transistor, the third transistor is a pull-up transistor in the first SRAM cell, and wherein the fourth transistor is a pass-gate transistor, the fifth transistor is a pull-down transistor, the sixth transistor is a pull-up transistor in the second SRAM cell. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a ratio of the sixth channel width to the third channel width is in a range of 1.05 to 1.5. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a ratio of the fifth channel width to the second channel width is in a range of 1.2 to 5. 
     
     
         6 . The semiconductor device of  claim 1 , wherein a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the second channel width is greater than the third channel width. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the first channel width is greater than the third channel width. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the fourth channel width is greater than the sixth channel width. 
     
     
         10 . The semiconductor device of  claim 9 , wherein a ratio of the fourth channel width to the sixth channel width is in a range of 1.5 to 5. 
     
     
         11 . A semiconductor device, comprising:
 a first active region extending along a first direction, the first active region including a first sidewall spaced apart from a second sidewall along a second direction perpendicular to the first direction for a first distance;   a first gate structure extending along the second direction and across the first active region, the first gate structure including a first gate dielectric layer and a first gate electrode disposed on the first gate dielectric layer;   a first gate spacer extending along a sidewall of the first gate structure, a dielectric constant of the first gate dielectric layer being greater than a dielectric constant of the first gate spacer;   a second active region extending along the first direction, the second active region abutting the first active region, the second active region including a first sidewall spaced apart from a second sidewall along the second direction for a second distance;   a second gate structure extending along the second direction and across the second active region, the second gate structure including a second gate dielectric layer and a second gate electrode disposed on the second gate dielectric layer; and   a second gate spacer extending along a sidewall of the second gate structure, a dielectric constant of the second gate dielectric layer being greater than a dielectric constant of the second gate spacer,   wherein:
 the first distance is smaller than the second distance, 
 with respect to a center line of the first active region extending along the first direction and through the second active region, the first sidewall of the first active region and the first sidewall of the second active region are disposed on a first side of the center line, and the second sidewall of the first active region and the second sidewall of the second active region are disposed on a second side of the center line, the first side opposing the second side, 
 the first sidewall of the first active region is offset from the first sidewall of the second active region along the second direction, and 
 the second sidewall of the first active region is offset from the second sidewall of the second active region along the second direction. 
   
     
     
         12 . The semiconductor device of  claim 11 , wherein a ratio of the second distance to the first distance is in a range of 1.05 to 1.5. 
     
     
         13 . The semiconductor device of  claim 11 , further comprising:
 a third active region extending along the first direction and spaced apart from the second active region along the second direction, the second gate structure across the third active region, the third active region including a first sidewall spaced apart from a second sidewall along the second direction for a third distance, the third distance being smaller than the second distance and not larger than the first distance.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the third distance equals the first distance. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the third distance is smaller than the first distance. 
     
     
         16 . The semiconductor device of  claim 13 , wherein the first gate structure and the first active region forms a first n-type transistor, the second gate structure and the second active region forms a second n-type transistor, and the second gate structure and the third active region forms a p-type transistor. 
     
     
         17 . A semiconductor device, comprising:
 first and second active regions extending lengthwise along a first direction and spaced apart from each other along a second direction different from the first direction;   a first gate structure extending lengthwise along the second direction and across a first portion of the first active region; and   a second gate structure extending lengthwise along the second direction and across the second active region and a second portion of the first active region,   wherein:
 the first gate structure and the second gate structure comprise a titanium-containing material, 
 the first portion of the first active region has a first width, 
 the second portion of the first active region has a second width greater than the first width, 
 the second active region has a third width less than the first width, 
 the first active region has a first sidewall opposing a second sidewall along the second direction, and 
 each of the first and second sidewalls of the first active region has a step profile. 
   
     
     
         18 . The semiconductor device of  claim 17 , wherein a ratio of the second width to the first width is in a range of 1.05 to 1.5. 
     
     
         19 . The semiconductor device of  claim 17 , further comprising:
 third and fourth active regions extending lengthwise along the first direction and spaced apart from each other along the second direction;   a third gate structure extending lengthwise along the second direction and across a first portion of the third active region; and   a fourth gate structure extending lengthwise along the second direction and across the fourth active region and a second portion of the third active region,   wherein:
 the third gate structure and the fourth gate structure comprise the titanium-containing material, 
 the first portion of the third active region has a fourth width, 
 the second portion of the third active region has a fifth width equal to the fourth width, 
 the fourth active region has a sixth width smaller than the fifth width but larger than the third width. 
   
     
     
         20 . The semiconductor device of  claim 19 , wherein a ratio of the sixth width to the third width is in a range of 1.05 to 1.5.