Slice-based memory channel power control

Abstract

An apparatus includes a plurality of memory channels to a memory. The plurality of memory channels include a first slice and at least a second slice that is distinct from the first slice. The apparatus further includes power control circuitry coupled to the plurality of memory channels. The power control circuitry is configured to adjust, in accordance with a power collapse trigger condition associated with the first slice, operation of the first slice from a first mode of operation to a second mode of operation independently of the second slice. The first mode of operation is associated with a first power consumption level that is greater than a second power consumption level associated with the second mode of operation.

1 . An apparatus comprising:
 a plurality of memory channels to a memory, the plurality of memory channels including a first slice and at least a second slice that is distinct from the first slice;   power control circuitry coupled to the plurality of memory channels and configured to adjust, in accordance with a power collapse trigger condition associated with the first slice, operation of the first slice from a first mode of operation to a second mode of operation independently of the second slice, wherein the first mode of operation is associated with a first power consumption level that is greater than a second power consumption level associated with the second mode of operation; and   circuitry coupled to the plurality of memory channels and configured to perform interleaving of memory access operations to the first slice and the second slice on a per-slice basis.   
     
     
         2 . The apparatus of  claim 1 , wherein the power control circuitry is further configured to:
 detect a power resume trigger condition associated with the first slice; and   based on detecting the power resume trigger condition, adjust operation of the first slice from the second mode to the first mode independently of the second slice.   
     
     
         3 . The apparatus of  claim 1 , wherein the first slice and the second slice each include a system level cache (SLC) controller, a memory controller coupled to the SLC controller, and a physical interface between the memory controller and the memory. 
     
     
         4 . The apparatus of  claim 1 , wherein the plurality of memory channels are coupled to one or more power supply nodes, and wherein the power control circuitry includes, for each slice of the plurality of memory channels, a power gating circuit that is coupled to the one or more power supply nodes and that is configured to selectively disconnect the slice from the one or more power supply nodes. 
     
     
         5 . The apparatus of  claim 1 , further comprising a power collapse manager that is coupled to the power control circuitry and that is configured to detect the power collapse trigger condition. 
     
     
         6 . The apparatus of  claim 5 , wherein the power collapse manager is further configured to detect the power collapse trigger condition based on one or more of a software workload of a processor that is associated with the first slice, a hardware usage level associated with the first slice, or a vote metric associated with one or more processors including the processor. 
     
     
         7 . The apparatus of  claim 1 , wherein the circuitry includes a memory network-on-chip (NoC) coupled to the plurality of memory channels and to the memory, and wherein the memory NoC is configured to operate in accordance with a slice-based interleaving scheme. 
     
     
         8 . The apparatus of  claim 7 , wherein the slice-based interleaving scheme enables an intra-slice interleaving of the memory access operations within the first slice and disables an inter-slice interleaving of the memory access operations between the first slice and the second slice. 
     
     
         9 . The apparatus of  claim 1 , wherein the memory corresponds to a hybrid memory including a first memory of a first memory type and a second memory of a second memory type different than the first memory type, wherein the first slice is associated with the first memory, and wherein the second slice is associated with the second memory. 
     
     
         10 . A method comprising:
 accessing a memory using a plurality of memory channels, the plurality of memory channels including a first slice and at least a second slice that is distinct from the first slice, wherein accessing the memory includes performing interleaving of memory access operations to the first slice and the second slice on a per-slice basis; and   in accordance with a power collapse trigger condition associated with the first slice, adjusting operation of the first slice from a first mode of operation to a second mode of operation independently of the second slice,   wherein the first mode of operation is associated with a first power consumption level that is greater than a second power consumption level associated with the second mode of operation.   
     
     
         11 . The method of  claim 10 , further comprising:
 detecting a power resume trigger condition associated with the first slice; and   based on detecting the power resume trigger condition, adjusting operation of the first slice from the second mode to the first mode independently of the second slice.   
     
     
         12 . The method of  claim 10 , wherein the first slice and the second slice each include a system level cache (SLC) controller, a memory controller coupled to the SLC controller, and a physical interface between the memory controller and the memory. 
     
     
         13 . The method of  claim 10 , further comprising, for each slice of the plurality of memory channels, selectively disconnecting the slice from one or more power supply nodes using power control circuitry. 
     
     
         14 . The method of  claim 10 , further comprising detecting the power collapse trigger condition using a power collapse manager. 
     
     
         15 . The method of  claim 14 , wherein the power collapse trigger condition is detected based on one or more of a software workload of a processor that is associated with the first slice, a hardware usage level associated with the first slice, or a vote metric associated with one or more processors including the processor. 
     
     
         16 . The method of  claim 10 , wherein the memory is accessed via a memory network-on-chip (NoC) and in accordance with a slice-based interleaving scheme. 
     
     
         17 . The method of  claim 16 , wherein the slice-based interleaving scheme enables an intra-slice interleaving of the memory access operations within the first slice and disables an inter-slice interleaving of the memory access operations between the first slice and the second slice. 
     
     
         18 . The method of  claim 10 , wherein the memory corresponds to a hybrid memory including a first memory of a first memory type and a second memory of a second memory type different than the first memory type, wherein the first slice is associated with the first memory, and wherein the second slice is associated with the second memory. 
     
     
         19 . A non-transitory computer-readable medium storing instructions executable by one or more processors to initiate, perform, or control operations, the operations comprising:
 accessing a memory using a plurality of memory channels, the plurality of memory channels including a first slice and at least a second slice that is distinct from the first slice wherein accessing the memory includes performing interleaving of memory access operations to the first slice and the second slice on a per-slice basis;   in accordance with a power collapse trigger condition associated with the first slice, adjusting operation of the first slice from a first mode of operation to a second mode of operation independently of the second slice,   wherein the first mode of operation is associated with a first power consumption level that is greater than a second power consumption level associated with the second mode of operation.   
     
     
         20 . The non-transitory computer-readable medium of  claim 19 , wherein the operations further comprise:
 detecting a power resume trigger condition associated with the first slice; and   based on detecting the power resume trigger condition, adjusting operation of the first slice from the second mode to the first mode independently of the second slice.