Memory device and electronic apparatuses including the same

Abstract

A memory device includes a pillar, a gate oxide layer surrounding a side surface of the pillar, a resistance change layer surrounding a side surface of the gate oxide layer, and a plurality of interlayer isolation layers and a plurality of gate electrodes surrounding a side surface of the resistance change layer, the plurality of interlayer isolation layers and the plurality of gate electrodes alternating along a surface of the resistance change layer.

What is claimed is: 
     
         1 . A memory device comprising:
 a pillar;   a gate oxide layer surrounding a side surface of the pillar;   a resistance change layer surrounding a side surface of the gate oxide layer; and   a plurality of interlayer isolation layers and a plurality of gate electrodes surrounding a side surface of the resistance change layer, the plurality of interlayer isolation layers and the plurality of gate electrodes alternating along a surface of the resistance change layer.   
     
     
         2 . The memory device of  claim 1 , wherein the resistance change layer comprises a trap site. 
     
     
         3 . The memory device of  claim 1 , wherein the resistance change layer comprises metal oxide or nitride. 
     
     
         4 . The memory device of  claim 3 , wherein the metal oxide comprises TaOx, HfOx, or TiOx. 
     
     
         5 . The memory device of  claim 3 , wherein the nitride comprises SiNx. 
     
     
         6 . The memory device of  claim 1 , wherein a thickness of the resistance change layer is 10 nm or less. 
     
     
         7 . The memory device of  claim 1 , wherein the gate electrodes comprise doped silicon or a metal material. 
     
     
         8 . The memory device of  claim 1 , wherein the interlayer isolation layers comprise silicon oxide, silicon nitride, silicon oxynitride, or alumina. 
     
     
         9 . The memory device of  claim 1 , wherein a thickness of each of the interlayer isolation layers is 5 nm or less. 
     
     
         10 . The memory device of  claim 1 , wherein the gate oxide layer comprises silicon oxide. 
     
     
         11 . The memory device of  claim 1 , wherein a thickness of the gate oxide layer is 10 nm or less. 
     
     
         12 . The memory device of  claim 1 , further comprising:
 an insulating layer between the gate electrodes and the resistance change layer.   
     
     
         13 . The memory device of  claim 12 , wherein the insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, or alumina. 
     
     
         14 . The memory device of  claim 12 , wherein a thickness of the insulating layer is 2 nm or less. 
     
     
         15 . A memory device comprising:
 a plurality of cell strings; and   a plurality of interlayer isolation layers and a plurality of gate electrodes surrounding side surfaces of the plurality of cell strings, the plurality of interlayer isolation layers and the plurality of gate electrodes alternating along the side surfaces of the plurality of cell strings,   wherein each of the plurality of cell strings includes a pillar, a gate oxide layer surrounding a side surface of the pillar, and a resistance change layer surrounding a side surface of the gate oxide layer.   
     
     
         16 . The memory device of  claim 15 , wherein the resistance change layer comprises a trap site. 
     
     
         17 . The memory device of  claim 15 , wherein the resistance change layer comprises metal oxide or nitride. 
     
     
         18 . The memory device of  claim 15 , wherein each of the plurality of cell strings further includes an insulating layer surrounding a side surface of the resistance change layer. 
     
     
         19 . The memory device of  claim 18 , wherein the insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, or alumina. 
     
     
         20 . An electronic apparatus comprising the memory device according to  claim 1 .