Back-trench isolation structure

Abstract

The present disclosure relates to an image sensor integrated chip (IC). The image sensor IC includes one or more interconnects arranged within an inter-level dielectric (ILD) structure on a first side of a substrate. An image sensing element is arranged within the substrate. Sidewalls of the substrate form one or more trenches extending from a second side of the substrate to within the substrate on opposing sides of the image sensing element. A dielectric structure is arranged on the sidewalls of the substrate that form the one or more trenches. A conductive core is arranged within the one or more trenches and is laterally separated from the substrate by the dielectric structure. The conductive core is electrically coupled to the one or more interconnects.

1 . An image sensor integrated chip (IC), comprising:
 one or more interconnects arranged within an inter-level dielectric (ILD) structure on a first side of a substrate;   an image sensing element arranged within the substrate, wherein sidewalls of the substrate form one or more trenches extending from a second side of the substrate to within the substrate on opposing sides of the image sensing element;   a dielectric structure arranged on the sidewalls of the substrate that form the one or more trenches;   a conductive core arranged within the one or more trenches and laterally separated from the substrate by the dielectric structure; and   wherein the conductive core is electrically coupled to the one or more interconnects.   
     
     
         2 . The image sensor IC of  claim 1 , further comprising:
 one or more gate structures arranged along the first side of the substrate, wherein the conductive core contacts the one or more gate structures.   
     
     
         3 . The image sensor IC of  claim 2 , wherein the one or more gate structures are directly between additional sidewalls of the substrate. 
     
     
         4 . The image sensor IC of  claim 2 , wherein the conductive core physically contacts a surface of the one or more gate structures that faces away from the ILD structure. 
     
     
         5 . The image sensor IC of  claim 1 , wherein the conductive core vertically protrudes outward from the first side of the substrate to physically contact the one or more interconnects. 
     
     
         6 . The image sensor IC of  claim 1 , further comprising:
 a biasing source coupled to the conductive core by way of the one or more interconnects, wherein the biasing source is configured to selectively apply a bias voltage to the conductive core.   
     
     
         7 . The image sensor IC of  claim 1 , wherein the conductive core extends vertically past a bottom of the dielectric structure that faces the ILD structure and that is within the one or more trenches. 
     
     
         8 . The image sensor IC of  claim 1 , wherein the conductive core vertically protrudes outward past an upper surface of the substrate that faces away from the ILD structure. 
     
     
         9 . The image sensor IC of  claim 1 , further comprising:
 a grid structure arranged directly over the conductive core, wherein the dielectric structure is arranged between a top of the conductive core and a bottom of the grid structure.   
     
     
         10 . An image sensor integrated chip (IC), comprising:
 one or more interconnects arranged within an ILD structure on a first side of a substrate;   an image sensing element arranged within the substrate;   a conductive core extending from a second side of the substrate to within the substrate on opposing sides of the image sensing element, wherein the conductive core is electrically coupled to the one or more interconnects; and   a biasing source coupled to the conductive core by way of the one or more interconnects, wherein the biasing source is configured to selectively apply a bias voltage to the conductive core.   
     
     
         11 . The image sensor IC of  claim 10 , wherein the conductive core continuously extends from within the substrate to a non-zero distance past the second side of the substrate. 
     
     
         12 . The image sensor IC of  claim 10 , wherein the substrate further comprises a plurality of angled sidewalls that define one or more triangular shaped cavities within the second side of the substrate, the one or more triangular shaped cavities being directly vertically over the image sensing element and laterally between sidewalls of the conductive core. 
     
     
         13 . The image sensor IC of  claim 10 , further comprising:
 one or more gate structures arranged along the first side of the substrate and electrically coupled to the one or more interconnects, wherein the conductive core extends into the one or more gate structures.   
     
     
         14 . The image sensor IC of  claim 13 ,
 wherein the one or more gate structures comprise a gate electrode and a gate dielectric that separates the gate electrode from the substrate; and   wherein the conductive core extends through the gate dielectric to physically contact the gate electrode.   
     
     
         15 . The image sensor IC of  claim 10 , wherein the conductive core wraps around the image sensing element in a closed and continuously loop as viewed in a top-view. 
     
     
         16 . The image sensor IC of  claim 10 , further comprising:
 one or more absorption enhancement layers arranged along the second side of the substrate, wherein the substrate comprises angled sidewalls that are directly over the image sensing element and wherein the one or more absorption enhancement layers line the angled sidewalls; and   wherein the conductive core is arranged within one or more trenches defined by sidewalls of the substrate, the one or more absorption enhancement layers being entirely outside of one or more trenches.   
     
     
         17 - 20 . (canceled) 
     
     
         21 . The image sensor IC of  claim 1 , wherein the conductive core protrudes outward from the second side of the substrate to a top surface that is a non-zero distance over the second side of the substrate in a cross-sectional view, the top surface of the conductive core comprising a first segment and a second segment protruding outward from a side of the first segment in a top-view. 
     
     
         22 . An integrated chip structure, comprising:
 one or more interconnects within an inter-level dielectric (ILD) structure arranged along a first side of a substrate, wherein the substrate has sidewalls that form one or more trenches extending from a second side of the substrate to within the substrate along opposing sides of a pixel region;   a conductive core arranged within the one or more trenches, wherein the conductive core extends from over the second side of the substrate to be electrically coupled to the one or more interconnects;   one or more dielectric materials arranged laterally between the conductive core and the sidewalls of the substrate; and   a metal grid structure arranged directly above the conductive core, wherein the one or more dielectric materials separate a top of the conductive core and a bottom of the metal grid structure.   
     
     
         23 . The integrated chip structure of  claim 22 , further comprising:
 a gate structure arranged along the first side of the substrate and being electrically connected to the one or more interconnects, wherein the conductive core electrically contacts the gate structure.   
     
     
         24 . The integrated chip structure of  claim 22 , further comprising:
 a recessed gate structure comprising a first segment arranged along the first side of the substrate and a second segment protruding outward from a horizontally extending surface of the first segment to within the substrate, wherein the conductive core contacts the second segment.