Cross-temperature compensation in a memory sub-system

Abstract

Control logic in a memory device receives, from a requestor, a request to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored and performs, using previously configured read operation parameters, a first read operation to read the data and a write temperature associated with the data from the memory array. The control logic determines whether the previously configured read operation parameters satisfy a temperature criterion and responsive to determining that the previously configured read operation parameters do not satisfy the temperature criterion, configures the memory device with updated read operation parameters, and performs, using the updated read operation parameters, a second read operation to read the data from the memory array.

What is claimed is: 
     
         1 . A memory device comprising:
 a memory array; and   control logic, operatively coupled with the memory array, to perform operations comprising:
 providing data read from the memory array using initial read operation parameters to a requestor; 
 receiving, from the requestor, a request to re-read the data from the memory array; and 
 performing a read operation to re-read the data from the memory array using updated read operation parameters based at least in part on a write temperature stored with the data in the memory array. 
   
     
     
         2 . The memory device of  claim 1 , wherein the control logic is to perform operations further comprising:
 providing the data re-read from the memory array using the updated read operation parameters to the requestor.   
     
     
         3 . The memory device of  claim 1 , wherein the control logic is to perform operations further comprising:
 determining a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to re-read the data is received.   
     
     
         4 . The memory device of  claim 3 , wherein the updated read operation parameters are determined based on at least one of the write temperature or the cross-temperature. 
     
     
         5 . The memory device of  claim 4 , wherein the updated read operation parameters comprise a read voltage level adjusted by a corresponding offset amount. 
     
     
         6 . The memory device of  claim 1 , wherein the request to re-read the data from the memory array is received responsive to the requestor determining that an error rate in the data read using the initial read operation parameters exceeds an error correction capability of the requestor. 
     
     
         7 . The memory device of  claim 1 , wherein the data is stored in a segment of the memory array, and wherein the write temperature is stored in a flag byte associated with the segment. 
     
     
         8 . A method comprising:
 providing data read from a memory device using initial read operation parameters to a requestor;   receiving, from the requestor, a request to re-read the data from the memory device; and   performing a read operation to re-read the data from the memory device using updated read operation parameters based at least in part on a write temperature stored with the data in the memory device.   
     
     
         9 . The method of  claim 8 , further comprising:
 providing the data re-read from the memory device using the updated read operation parameters to the requestor.   
     
     
         10 . The method of  claim 8 , further comprising:
 determining a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to re-read the data is received.   
     
     
         11 . The method of  claim 10 , wherein the updated read operation parameters are determined based on at least one of the write temperature or the cross-temperature. 
     
     
         12 . The method of  claim 11 , wherein the updated read operation parameters comprise a read voltage level adjusted by a corresponding offset amount. 
     
     
         13 . The method of  claim 8 , wherein the request to re-read the data from the memory device is received responsive to the requestor determining that an error rate in the data read using the initial read operation parameters exceeds an error correction capability of the requestor. 
     
     
         14 . The method of  claim 8 , wherein the data is stored in a segment of the memory device, and wherein the write temperature is stored in a flag byte associated with the segment. 
     
     
         15 . A memory device comprising:
 a memory array; and   control logic, operatively coupled with the memory array, to perform operations comprising:
 providing data read from a segment of the memory array using initial read operation parameters to a requestor; 
 receiving, from the requestor, a request to re-read the data from the segment of the memory array; and 
 performing a read operation to re-read the data from the segment of the memory array using updated read operation parameters based at least in part on a write temperature stored in a flag byte associated with the segment of the memory array. 
   
     
     
         16 . The memory device of  claim 15 , wherein the control logic is to perform operations further comprising:
 providing the data re-read from the segment of the memory array using the updated read operation parameters to the requestor.   
     
     
         17 . The memory device of  claim 15 , wherein the control logic is to perform operations further comprising:
 determining a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to re-read the data is received.   
     
     
         18 . The memory device of  claim 17 , wherein the updated read operation parameters are determined based on at least one of the write temperature or the cross-temperature. 
     
     
         19 . The memory device of  claim 18 , wherein the updated read operation parameters comprise a read voltage level adjusted by a corresponding offset amount. 
     
     
         20 . The memory device of  claim 15 , wherein the request to re-read the data from the segment of the memory array is received responsive to the requestor determining that an error rate in the data read using the initial read operation parameters exceeds an error correction capability of the requestor.