Semiconductor devices with superlattice layers in source/drain regions and manufacturing methods thereof

Abstract

The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a first stack over a substrate and a second stack over the first stack. The first stack includes semiconductor layers interleaved by dielectric layers. The second stack includes channel layers interleaved by sacrificial layers. The method also includes patterning the second stack to form a fin-shape structure, recessing a portion of the fin-shape structure to form a recess exposing a top surface of the first stack, epitaxially growing an epitaxial feature directly from the top surface of the first stack, removing the sacrificial layers to release the channel layers, and forming a gate structure wrapping around each of the channel layers.

What is claimed is: 
     
         1 . A method, comprising:
 forming a stack over a substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;   patterning the stack to form a fin-shape structure, the fin-shape structure comprising a channel region and a source/drain region;   forming a dummy gate stack over the channel region of the fin-shape structure;   depositing a gate spacer layer over the dummy gate stack;   recessing the source/drain region to form a source/drain trench that exposes a top surface of the substrate, sidewalls of the channel layers, and sidewalls of the sacrificial layers;   depositing a superlattice in the source/drain trench, the superlattice including at least one dielectric layer sandwiched between two semiconductor layers;   epitaxially growing a source/drain feature from the superlattice and the sidewalls of the channel layers;   removing the dummy gate stack;   releasing the channel layers in the channel region; and   forming a metal gate structure wrapping around each of the channel layers.   
     
     
         2 . The method of  claim 1 , wherein the depositing of the superlattice includes an epitaxial growing process. 
     
     
         3 . The method of  claim 1 , wherein each layer in the superlattice maintains a same crystalline orientation as the top surface of the substrate. 
     
     
         4 . The method of  claim 1 , wherein the two semiconductor layers of the superlattice are crystalline silicon layers. 
     
     
         5 . The method of  claim 1 , wherein the dielectric layer of the superlattice includes oxygen doped silicon or nitrogen doped silicon. 
     
     
         6 . The method of  claim 1 , wherein the dielectric layer is a monolayer. 
     
     
         7 . The method of  claim 1 , further comprising:
 laterally recessing the sidewalls of the sacrificial layers to form a plurality of inner spacer recesses; and   forming a plurality of inner spacer features in the inner spacer recesses,   wherein a top surface of the superlattice intersects a sidewall of a bottommost one of the inner spacer features.   
     
     
         8 . The method of  claim 1 , further comprising:
 prior to the depositing of the superlattice, forming an undoped epitaxial layer in the source/drain trench, wherein the superlattice is in contact with a top surface of the undoped epitaxial layer.   
     
     
         9 . The method of  claim 1 , further comprising:
 after the depositing of the superlattice, forming an undoped epitaxial layer in the source/drain trench, wherein the superlattice is in contact with a bottom surface of the undoped epitaxial layer.   
     
     
         10 . A method, comprising:
 forming a first stack over a substrate, the first stack comprising a plurality of semiconductor layers interleaved by a plurality of dielectric layers;   forming a second stack over the first stack, the second stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;   patterning the second stack to form a fin-shape structure;   recessing a portion of the fin-shape structure to form a recess exposing a top surface of the first stack;   epitaxially growing an epitaxial feature directly from the top surface of the first stack;   removing the sacrificial layers to release the channel layers; and   forming a gate structure wrapping around each of the channel layers.   
     
     
         11 . The method of  claim 10 , wherein the gate structure is in contact with the first stack. 
     
     
         12 . The method of  claim 10 , wherein each of the dielectric layers includes one or more monolayers of silicon dioxide or silicon nitride. 
     
     
         13 . The method of  claim 10 , wherein each of the semiconductor layers includes crystalline silicon. 
     
     
         14 . The method of  claim 10 , further comprising:
 laterally recessing the sacrificial layers to form a plurality of cavities; and   forming a plurality of dielectric features in the cavities,   wherein the top surface of the first stack is in direct contact with a bottommost one of the dielectric features.   
     
     
         15 . The method of  claim 10 , wherein a thickness of the first stack ranges from about 2 nm to about 10 nm. 
     
     
         16 . A semiconductor device, comprising:
 a plurality of nanostructures vertically stacked above a substrate;   a gate structure wrapping around each of the nanostructures;   a source/drain feature abutting the nanostructures; and   a superlattice interposing the substrate and a bottom surface of the source/drain feature, wherein the superlattice includes at least one dielectric layer sandwiched between two semiconductor layers.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the substrate includes a crystalline structure, and the dielectric layer and the semiconductor layers of the superlattice maintain a same crystalline orientation as the substrate. 
     
     
         18 . The semiconductor device of  claim 16 , wherein the dielectric layer includes one or more monolayers of oxygen doped silicon or nitrogen doped silicon, and the semiconductor layers each include crystalline silicon. 
     
     
         19 . The semiconductor device of  claim 16 , wherein the superlattice extends to a position directly under the gate structure. 
     
     
         20 . The semiconductor device of  claim 16 , further comprising:
 an undoped epitaxial layer under the source/drain feature, wherein the undoped epitaxial layer is in contact with the superlattice.