Semiconductor structure with gate isolation layer and manufacturing method thereof

Abstract

A method includes forming a lower semiconductor region, forming an upper semiconductor region overlapping the lower semiconductor region, forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region, respectively, forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric, etching back the lower gate electrode, forming a gate isolation layer on the lower gate electrode that has been etched back, and forming an upper gate electrode over the gate isolation layer. The upper gate electrode is on the upper gate dielectric.

What is claimed is: 
     
         1 . A method comprising:
 forming a lower semiconductor region;   forming an upper semiconductor region overlapping the lower semiconductor region;   forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region, respectively;   forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric;   etching back the lower gate electrode;   forming a gate isolation layer on the lower gate electrode that has been etched back; and   forming an upper gate electrode over the gate isolation layer, wherein the upper gate electrode is on the upper gate dielectric; and   patterning the gate isolation layer, wherein the forming the gate isolation layer comprises:
 depositing a dielectric layer; 
 planarizing the dielectric layer; and 
 etching back the dielectric layer, wherein a remaining portion of the dielectric layer forms the gate isolation layer.