Semiconductor memory device

Abstract

Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral structure, a first upper cell structure on the peripheral structure, and a first lower cell structure on an opposite side of the peripheral structure from the first upper cell structure, wherein each of the first upper cell structure and the first lower cell structure includes a first active pattern perpendicular to an upper surface of the peripheral structure, a first word line adjacent to a side surface of the first active pattern and extending in a first direction parallel to the upper surface of the peripheral structure, and a first bit line electrically connected to a first end of the first active pattern and extending in a second direction intersecting the first direction.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a peripheral structure;   a first upper cell structure on the peripheral structure; and   a first lower cell structure on an opposite side of the peripheral structure from the first upper cell structure,   wherein each of the first upper cell structure and the first lower cell structure comprises:   a first active pattern perpendicular to an upper surface of the peripheral structure;   a first word line adjacent to a side surface of the first active pattern and extending in a first direction parallel to the upper surface of the peripheral structure; and   a first bit line electrically connected to a first end of the first active pattern and extending in a second direction intersecting the first direction.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the peripheral structure comprises:
 a peripheral substrate;   peripheral transistors and peripheral lines on an upper surface of the peripheral substrate;   a peripheral interlayer insulating layer on the peripheral transistors and the peripheral lines;   a peripheral lower insulating layer on a lower surface of the peripheral substrate;   a peripheral upper pad at an upper end of the peripheral interlayer insulating layer; and   a through via extending into the peripheral substrate and electrically connected to one of the peripheral lines.   
     
     
         3 . The semiconductor memory device of  claim 2 , wherein the first upper cell structure further comprises a first upper cell interlayer insulating layer and a first upper cell pad at a lower end of the first upper cell interlayer insulating layer and in contact with the peripheral upper pad, and
 wherein the first lower cell structure further comprises a first lower cell interlayer insulating layer and a first lower cell line in the first lower cell interlayer insulating layer and electrically connected to the through via.   
     
     
         4 . The semiconductor memory device of  claim 3 , wherein the first lower cell structure further comprises a first lower cell pad at an upper end of the first lower cell interlayer insulating layer,
 wherein the peripheral structure further comprises a peripheral lower pad at a lower end of the peripheral lower insulating layer and in contact with the first lower cell pad, and   wherein the through via extends into the peripheral lower insulating layer and is in contact with the peripheral lower pad.   
     
     
         5 . The semiconductor memory device of  claim 1 , wherein each of the first upper cell structure and the first lower cell structure further comprises:
 a first electrode electrically connected to a second end of the first active pattern;   a dielectric layer on the first electrode; and   a second electrode on the dielectric layer,   wherein the second end is opposite to the first end of the first active pattern, and   wherein the first bit line is closer to the peripheral structure than the first electrode in each of the first upper cell structure and the first lower cell structure.   
     
     
         6 . The semiconductor memory device of  claim 1 , wherein the peripheral structure comprises a first upper sense amplifier, a first lower sense amplifier, a first upper word line driver, and a first lower word line driver,
 wherein an end of the first bit line of the first upper cell structure is electrically connected to the first upper sense amplifier,   wherein an end of the first word line of the first upper cell structure is electrically connected to the first upper word line driver,   wherein an end of the first bit line of the first lower cell structure is electrically connected to the first lower sense amplifier, and   wherein an end of the first word line of the first lower cell structure is electrically connected to the first lower word line driver.   
     
     
         7 . The semiconductor memory device of  claim 1 , further comprising:
 a second upper cell structure on the first upper cell structure; and   a second lower cell structure on an opposite side of the first lower cell structure from the peripheral structure,   wherein each of the second upper cell structure and the second lower cell structure comprises:   a second active pattern perpendicular to the upper surface of the peripheral structure;   a second word line adjacent to a side surface of the second active pattern and extending in the first direction; and   a second bit line electrically connected to a first end of the second active pattern and extending in the second direction.   
     
     
         8 . The semiconductor memory device of  claim 1 , further comprising a support substrate on an opposite side of the first lower cell structure from the peripheral structure. 
     
     
         9 . The semiconductor memory device of  claim 1 , wherein the first upper cell structure further comprises an external connection pad at an upper end of the first upper cell structure. 
     
     
         10 . A semiconductor memory device comprising:
 a peripheral structure;   at least one upper cell structure on the peripheral structure; and   at least one lower cell structure on an opposite side of the peripheral structure from the upper cell structure,   wherein each of the upper cell structure and the lower cell structure comprises an array of memory cells, and   wherein the peripheral structure comprises:   a peripheral substrate;   peripheral transistors and peripheral lines on an upper surface of the peripheral substrate;   a peripheral interlayer insulating layer on the peripheral transistors and the peripheral lines;   a peripheral lower insulating layer on a lower surface of the peripheral substrate;   a peripheral upper pad at an upper end of the peripheral interlayer insulating layer; and   a through via extending into the peripheral substrate and electrically connected to at least one of the peripheral lines.   
     
     
         11 . The semiconductor memory device of  claim 10 , wherein the upper cell structure further comprises an upper cell interlayer insulating layer and an upper cell pad at a lower end of the upper cell interlayer insulating layer and in contact with the peripheral upper pad, and
 wherein the lower cell structure further comprises a lower cell interlayer insulating layer and a lower cell line in the lower cell interlayer insulating layer and electrically connected to the through via.   
     
     
         12 . The semiconductor memory device of  claim 11 , wherein the lower cell structure further comprises a lower cell pad at an upper end of the lower cell interlayer insulating layer,
 wherein the peripheral structure further comprises a peripheral lower pad at a lower end of the peripheral lower insulating layer and in contact with the lower cell pad, and   wherein the through via extends into the peripheral lower insulating layer and is in contact with the peripheral lower pad.   
     
     
         13 . The semiconductor memory device of  claim 10 , wherein each of the memory cells comprises a cell transistor and a cell capacitor, and wherein the cell transistor is closer to the peripheral structure than the cell capacitor in each of the upper cell structure and the lower cell structure. 
     
     
         14 . The semiconductor memory device of  claim 10 , further comprising a support substrate on an opposite side of the lower cell structure from the peripheral structure. 
     
     
         15 . The semiconductor memory device of  claim 10 , wherein the upper cell structure further comprises an external connection pad at an upper end of the upper cell structure. 
     
     
         16 . A semiconductor memory device comprising:
 a peripheral structure;   a first upper cell structure on the peripheral structure; and   a first lower cell structure on an opposite side of the peripheral structure from the first upper cell structure,   wherein the peripheral structure comprises:   a peripheral substrate;   peripheral transistors and peripheral lines on an upper surface of the peripheral substrate;   a peripheral interlayer insulating layer on the peripheral transistors and the peripheral lines;   a peripheral lower insulating layer on a lower surface of the peripheral substrate;   a peripheral upper pad at an upper end of the peripheral interlayer insulating layer; and   a through via extending into the peripheral substrate and electrically connected to at least one of the peripheral lines,   wherein each of the first upper cell structure and the first lower cell structure comprises:   a first active pattern perpendicular to an upper surface of the peripheral structure;   a first word line adjacent to a side surface of the first active pattern and extending in a first direction parallel to the upper surface of the peripheral structure;   a first bit line electrically connected to a first end of the first active pattern and extending in a second direction intersecting the first direction;   a first electrode electrically connected to a second end of the first active pattern;   a dielectric layer on the first electrode; and   a second electrode on the dielectric layer,   wherein the second end is opposite to the first end of the first active pattern, and   wherein the first bit line is closer to the peripheral structure than the first electrode in each of the first upper cell structure and the first lower cell structure.   
     
     
         17 . The semiconductor memory device of  claim 16 , wherein the first upper cell structure further comprises a first upper cell interlayer insulating layer and a first upper cell pad at a lower end of the first upper cell interlayer insulating layer and in contact with the peripheral upper pad, and
 wherein the first lower cell structure further comprises a first lower cell interlayer insulating layer and a first lower cell line in the first lower cell interlayer insulating layer and electrically connected to the through via.   
     
     
         18 . The semiconductor memory device of  claim 17 , wherein the first lower cell structure further comprises a first lower cell pad at an upper end of the first lower cell interlayer insulating layer,
 wherein the peripheral structure further comprises a peripheral lower pad at a lower end of the peripheral lower insulating layer and in contact with the first lower cell pad, and   wherein the through via extends into the peripheral lower insulating layer and is in contact with the peripheral lower pad.   
     
     
         19 . The semiconductor memory device of  claim 16 , wherein the peripheral structure further comprises a first upper sense amplifier, a first lower sense amplifier, a first upper word line driver, and a first lower word line driver,
 wherein an end of the first bit line of the first upper cell structure is electrically connected to the first upper sense amplifier,   wherein an end of the first word line of the first upper cell structure is electrically connected to the first upper word line driver,   wherein an end of the first bit line of the first lower cell structure is electrically connected to the first lower sense amplifier, and   wherein an end of the first word line of the first lower cell structure is electrically connected to the first lower word line driver.   
     
     
         20 . The semiconductor memory device of  claim 16 , further comprising:
 a second upper cell structure on the first upper cell structure; and   a second lower cell structure on an opposite side of the first lower cell structure from the peripheral structure,   wherein each of the second upper cell structure and the second lower cell structure comprises:   a second active pattern perpendicular to the upper surface of the peripheral structure;   a second word line adjacent to a side surface of the second active pattern and extending in the first direction; and   a second bit line electrically connected to a first end of the second active pattern and extending in the second direction.