Semiconductor integrated circuit and equipment

Abstract

A semiconductor integrated circuit in which a plurality of logic circuits are arranged. Each logic circuit comprises n data holding circuits, a scan chain to transfer scan data, and a clock line including a plurality of clock buffers. The clock signal from the clock line is supplied to the n data holding circuits. In a forward direction from a first data holding circuit in the n data holding circuits to an nth data holding circuit in the holding circuits, the clock signal with a large delay amount is supplied from the clock line to a data holding circuit on a downstream side. The scan chain transfers the scan data in a backward direction from the nth data holding circuit to the first data holding circuit. The scan data is transferred between the logic circuits via a first delay adjusting unit.

What is claimed is: 
     
         1 . A semiconductor integrated circuit in which a plurality of logic circuits are arranged,
 each logic circuit comprising:   n data holding circuits configured to hold data;   a scan chain configured to transfer scan data; and   a clock line including a plurality of clock buffers configured to delay a clock signal,   wherein the clock signal is supplied from the clock line to the n data holding circuits,   in a forward direction from a first data holding circuit in the n data holding circuits to an nth data holding circuit in the n data holding circuits, the clock signal with a large delay amount is supplied from the clock line to a data holding circuit on a downstream side,   the scan chain is arranged to transfer the scan data in a backward direction from the nth data holding circuit to the first data holding circuit, and   the scan data is transferred between the logic circuits via a first delay adjusting unit.   
     
     
         2 . The circuit according to  claim 1 , wherein the first delay adjusting unit is a latch circuit, and the latch circuit delays an input to the latch circuit by a half period of the clock signal and outputs the input. 
     
     
         3 . The circuit according to  claim 1  comprising a logic circuit group formed by a predetermined number of the logic circuits, and
 the semiconductor integrated circuit further comprising a switching circuit configured to control transfer of the scan data between the logic circuit groups, and a control unit configured to control the switching circuit. 
 
     
     
         4 . The circuit according to  claim 3 , wherein the switching circuit controls whether to supply the scan data to the logic circuit group or bypass the logic circuit group. 
     
     
         5 . The circuit according to  claim 3 , wherein a second delay adjusting unit configured to delay the scan data is provided between the logic circuit groups. 
     
     
         6 . The circuit according to  claim 5 , wherein the second delay adjusting unit is a latch circuit, and the latch circuit delays an input by a half period of the clock signal and outputs the input. 
     
     
         7 . The circuit according to  claim 3 , wherein the switching circuit includes a multiplexer. 
     
     
         8 . The circuit according to  claim 1 , wherein the logic circuit operates as a ripple counter. 
     
     
         9 . The circuit according to  claim 8 , wherein the ripple counter forms a part of a filter configured to decrease the number of bits of data from an analog-to-digital converter. 
     
     
         10 . The circuit according to  claim 9 , wherein the analog-to-digital converter converts analog data from an image sensor into digital data. 
     
     
         11 . The circuit according to  claim 9 , wherein the analog to digital converter is a delta-sigma analog to digital converter. 
     
     
         12 . A semiconductor integrated circuit in which a logic circuit including n data holding circuits configured to hold data, a scan chain configured to transfer scan data, and a clock line including a plurality of clock buffers configured to delay a clock signal is arranged, wherein
 the n data holding circuits are connected to form a ripple counter configured to transfer data in a forward direction from a first data holding circuit to an nth data holding circuit,   the clock signal is supplied from the clock line to the n data holding circuits,   the clock signal with a large delay amount is supplied from the clock line to a data holding circuit on a downstream side in a forward direction, and   the scan chain is arranged to transfer the scan data in a backward direction from the nth data holding circuit to the first data holding circuit.   
     
     
         13 . Equipment comprising:
 a semiconductor integrated circuit defined in  claim 1 ; and   a processing apparatus configured to process an output signal from the semiconductor integrated circuit.