Redistribution substrate and semiconductor package including the same
Abstract
A redistribution substrate may include a first interconnection layer having a first insulating pattern, a first dummy pattern and a second dummy pattern, the first and second dummy patterns being in the first insulating pattern, and a second interconnection layer stacked on the first interconnection layer, the second interconnection layer having a second insulating pattern, a signal pattern and a power/ground pattern, the signal and power/ground patterns being in the second insulating pattern. The first dummy pattern may be located below the signal pattern, and the second dummy pattern may be located below the power/ground pattern. The first dummy pattern may include dot patterns, and the second dummy pattern may include a plate pattern.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A redistribution substrate, comprising:
a first interconnection layer having a first insulating pattern, a first dummy pattern and a second dummy pattern, the first dummy pattern and the second dummy pattern being in the first insulating pattern; and a second interconnection layer stacked on the first interconnection layer, the second interconnection layer having a second insulating pattern, a signal pattern and a power/ground pattern, the signal pattern and the power/ground pattern being in the second insulating pattern, wherein the first dummy pattern is located below the signal pattern, wherein the second dummy pattern is located below the power/ground pattern, wherein the first dummy pattern comprises dot patterns, wherein a diameter of each of the dot patterns of the first dummy pattern is between 1 μm and 30 μm, and wherein a distance between two adjacent dot patterns among the dot patterns of the first dummy pattern is between 1 μm and 50 μm.
2 . The redistribution substrate as claimed in claim 1 ,
wherein the second dummy pattern comprises a plate pattern.
3 . The redistribution substrate of claim 1 ,
wherein the dot patterns of the first dummy pattern are arranged in a first direction and a second direction, which are parallel to a top surface of the first interconnection layer and cross each other.
4 . The redistribution substrate of claim 3 ,
wherein an angle between the first direction and the second direction is 90° or 60°.
5 . The redistribution substrate of claim 1 ,
wherein the second dummy pattern comprises a plate pattern, and wherein the dot patterns of the first dummy pattern vertically overlap the signal pattern, and the plate pattern of the second dummy pattern vertically overlaps the power/ground pattern.
6 . The redistribution substrate of claim 1 ,
wherein a planar shape of each of the dot patterns of the first dummy pattern is a rectangular shape, a circular shape, or a cross shape.
7 . The redistribution substrate of claim 1 ,
wherein the second dummy pattern comprises a plate pattern, and wherein the plate pattern of the second dummy pattern comprises holes vertically penetrating the plate pattern, and the holes are arranged in a direction parallel to a top surface of the first interconnection layer.
8 . The redistribution substrate of claim 1 , further comprising:
a third interconnection layer having a third insulating pattern and a third dummy pattern in the third insulating pattern, wherein the first interconnection layer is stacked on the third interconnection layer, the third dummy pattern is located below the first dummy pattern, and the third dummy pattern comprises dot patterns.
9 . The redistribution substrate of claim 8 ,
wherein the dot patterns of the first dummy pattern do not vertically overlap the dot patterns of the third dummy pattern.
10 . The redistribution substrate of claim 9 ,
wherein the dot patterns of the first dummy pattern is arranged in a grid shape, wherein the dot patterns of the third dummy pattern is arranged in a grid shape, and wherein, when viewed in a plan view, one of the dot patterns of the third dummy pattern is located among four dot patterns of the first dummy pattern which are adjacent to each other.
11 . The redistribution substrate of claim 9 ,
wherein in a pair of dot patterns, which are respectively chosen from the first dummy pattern and the third dummy pattern, a distance from a center of a dot pattern chosen from the first dummy pattern to a side surface of a dot pattern chosen from the third dummy pattern has a value in a range from 1 μm to 50 μm, when viewed in a plan view.
12 . A redistribution substrate, comprising:
a first power/ground interconnection layer having a first insulating pattern, a first dummy pattern and a first power/ground pattern, the first dummy pattern and the first power/ground pattern being in the first insulating pattern; and a first signal interconnection layer stacked on the first power/ground interconnection layer, the first signal interconnection layer having a second insulating pattern, a second dummy pattern and a first signal pattern, the second dummy pattern and the first signal pattern being in the second insulating pattern, wherein the first dummy pattern is vertically overlapped with the first signal pattern, wherein the second dummy pattern is vertically overlapped with the first power/ground pattern, wherein the first dummy pattern comprises dot patterns, and wherein a planar shape of each of the dot patterns of the first dummy pattern is a rectangular shape, a circular shape, or a cross shape.
13 . The redistribution substrate of claim 12 ,
wherein the second dummy pattern comprises a plate pattern.
14 . The redistribution substrate of claim 12 ,
wherein the dot patterns of the first dummy pattern are arranged in a first direction and a second direction, which are parallel to a top surface of the first power/ground interconnection layer and cross each other.
15 . The redistribution substrate of claim 14 ,
wherein an angle between the first direction and the second direction is 90° or 60°.
16 . The redistribution substrate of claim 12 ,
wherein a diameter of the dot patterns of the first dummy pattern is between 1 μm and 30 μm.
17 . The redistribution substrate of claim 12 ,
wherein a distance between the dot patterns of the first dummy pattern is between and 1 μm and 50 μm.
18 . A redistribution substrate, comprising:
a first interconnection layer having a first insulating pattern, a first dummy pattern and a second dummy pattern, the first dummy pattern and the second dummy pattern being in the first insulating pattern; a second interconnection layer stacked on the first interconnection layer, the second interconnection layer having a second insulating pattern, a signal pattern and a power/ground pattern, the signal pattern and the power/ground pattern being in the second insulating pattern; and a third interconnection layer having a third insulating pattern and a third dummy pattern in the third insulating pattern, the first interconnection layer is stacked on the third interconnection layer, wherein the first dummy pattern is located below the signal pattern, wherein the second dummy pattern is located below the power/ground pattern, wherein the third dummy pattern is located below the first dummy pattern, wherein the first dummy pattern comprises dot patterns, wherein the third dummy pattern comprises dot patterns, wherein the dot patterns of the first dummy pattern is disposed to be horizontally shifted from the dot patterns of the third dummy pattern, and wherein, when viewed in a plan view, one of the dot patterns of the third dummy pattern is located the dot patterns of the first dummy pattern, which are adjacent to each other.
19 . The redistribution substrate as claimed in claim 18 ,
wherein the second dummy pattern comprises a plate pattern.
20 . The redistribution substrate of claim 18 ,
wherein the dot patterns of the first dummy pattern is arranged in a grid shape, wherein the dot patterns of the third dummy pattern is arranged in a grid shape, and wherein, when viewed in a plan view, one of the dot patterns of the third dummy pattern is located among four dot patterns of the first dummy pattern which are adjacent to each other.Join the waitlist — get patent alerts
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