US2025336609A1PendingUtilityA1

Multilayer ceramic capacitor

Assignee: MURATA MANUFACTURING COPriority: Apr 26, 2024Filed: Apr 9, 2025Published: Oct 30, 2025
Est. expiryApr 26, 2044(~17.7 yrs left)· nominal 20-yr term from priority
H01G 4/0085H01G 4/12H01G 4/2325H01G 4/30H01G 4/1227H01G 4/232H01G 4/012
72
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A multilayer ceramic capacitor includes an element body portion and an external electrode including an end-surface-side external electrode, a main-surface-side external electrode, a side-surface-side external electrode, and a ridgeline-portion-side external electrode. At least one of the main-surface-side external electrode and the side-surface-side external electrode includes a first projecting portion projecting toward a central portion of the element body portion in a length direction, relative to the ridgeline-portion-side external electrode. T0 is equal to or larger than about 2.5 mm, where T0 denotes a maximum distance between the first and second main surfaces. W0 is equal to or larger than about 2.5 mm, where W0 denotes a maximum distance between first and second side surfaces. 0.01×T0≤P1≤0.06×T0 and 0.01×W0≤P1≤0.06×W0 are satisfied, where P1 denotes a maximum projection length of the first projecting portion.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A multilayer ceramic capacitor comprising:
 an element body portion including a plurality of dielectric layers and a plurality of internal electrode layers layered in a layering direction, a first main surface and a second main surface opposed to each other in the layering direction, a first side surface and a second side surface opposed to each other in a width direction orthogonal or substantially orthogonal to the layering direction, and a first end surface and a second end surface opposed to each other in a length direction orthogonal or substantially orthogonal to the layering direction and the width direction; and   a first external electrode extending from the first end surface to each of the first main surface, the second main surface, the first side surface, and the second side surface and electrically connected to at least one layer of the plurality of internal electrode layers; wherein   the element body portion includes a ridgeline portion at which two surfaces adjacent to each other among the first main surface, the second main surface, the first side surface, and the second side surface meet each other;   the first external electrode includes:
 an end-surface-side first external electrode covering the first end surface; 
 a main-surface-side first external electrode connected to the end-surface-side first external electrode, and covering a portion of the first main surface and a portion of the second main surface; 
 a side-surface-side first external electrode connected to the end-surface-side first external electrode, and covering a portion of the first side surface and a portion of the second side surface; and 
 a ridgeline-portion-side first external electrode connected to the end-surface-side first external electrode, and covering the ridgeline portion; 
   at least one of the main-surface-side first external electrode and the side-surface-side first external electrode includes a first projecting portion projecting toward a central portion of the element body portion in the length direction, relative to the ridgeline-portion-side first external electrode;   T0 is equal to or larger than about 2.5 mm, where T0 denotes a maximum distance between the first main surface and the second main surface;   W0 is equal to or larger than about 2.5 mm, where W0 denotes a maximum distance between the first side surface and the second side surface; and   expressions (1) and (2) are satisfied:
   0.01× T 0≤ P 1≤0.06× T 0  (1),
 
   0.01× W 0≤ P 1≤0.06× W 0  (2),
 
   where P1 denotes a maximum projection length of the first projecting portion.   
     
     
         2 . The multilayer ceramic capacitor according to  claim 1 , wherein a condition of t1≤about 0.008×L0 is satisfied, where L0 denotes a maximum distance between the first end surface and the second end surface, and t1 denotes a maximum thickness of the end-surface-side first external electrode. 
     
     
         3 . The multilayer ceramic capacitor according to  claim 1 , wherein
 at least one of expressions (3) and (4) is satisfied:
   0.008× T 0≤ t 2  (3),
 
   0.008× W 0≤ t 3  (4),
 
   where t2 denotes a maximum thickness of the main-surface-side first external electrode and t3 denotes a maximum thickness of the side-surface-side first external electrode.   
     
     
         4 . The multilayer ceramic capacitor according to  claim 1 , wherein a rate of change between average dimensions in the length direction of adjacent portions of four portions of the main-surface-side first external electrode resulting from dividing the main-surface-side first external electrode into four equal or substantially equal portions in the width direction is not greater than about 20%. 
     
     
         5 . The multilayer ceramic capacitor according to  claim 1 , wherein a rate of change of average dimensions in the length direction of adjacent portions of four portions of the side-surface-side first external electrode resulting from dividing the side-surface-side first external electrode into four equal or substantially equal portions in the layering direction is not greater than about 20%. 
     
     
         6 . The multilayer ceramic capacitor according to  claim 1 , further comprising:
 a second external electrode extending from the second end surface to each of the first main surface, the second main surface, the first side surface, and the second side surface and electrically connected to at least one other layer of the plurality of internal electrode layers; wherein   the second external electrode includes:
 an end-surface-side second external electrode covering the second end surface; 
 a main-surface-side second external electrode connected to the end-surface-side second external electrode, and covering a portion of the first main surface and a portion of the second main surface; 
 a side-surface-side second external electrode connected to the end-surface-side second external electrode, and covering a portion of the first side surface and a portion of the second side surface; and 
 a ridgeline-portion-side second external electrode connected to the end-surface-side second external electrode, and covering the ridgeline portion; 
 at least one of the main-surface-side second external electrode and the side-surface-side second external electrode includes a second projecting portion projecting toward the central portion of the element body portion in the length direction, relative to the ridgeline-portion-side second external electrode; and 
   one of P1 and P2 is smaller than the other, where P2 denotes a maximum projection length of the second projecting portion.   
     
     
         7 . The multilayer ceramic capacitor according to  claim 1 , wherein a central portion of each of the first end surface and the second end surface is recessed. 
     
     
         8 . The multilayer ceramic capacitor according to  claim 1 , wherein a maximum distance between the first end surface and the second end surface of the element body is not less than about 3.05 mm and not greater than about 3.2 mm. 
     
     
         9 . The multilayer ceramic capacitor according to  claim 1 , wherein the first external electrode covers an entirety or substantially an entirety of the first end surface. 
     
     
         10 . The multilayer ceramic capacitor according to  claim 7 , wherein the second external electrode covers an entirety or substantially an entirety of the second end surface. 
     
     
         11 . The multilayer ceramic capacitor according to  claim 1 , wherein a total number of the plurality of internal electrode layers is not less than 300 and not greater than 600. 
     
     
         12 . The multilayer ceramic capacitor according to  claim 1 , wherein a thickness of each of the plurality of internal electrode layers is not less than about 0.9 μm and not greater than about 10 μm. 
     
     
         13 . The multilayer ceramic capacitor according to  claim 1 , wherein each of the plurality of internal electrode layers includes Ni, Cu, Ag, Pd, or Au or an alloy including at least one of Ni, Cu, Ag, Pd, or Au. 
     
     
         14 . The multilayer ceramic capacitor according to  claim 1 , wherein a total number of the plurality of dielectric layers includes not less than 300 and not greater than 800. 
     
     
         15 . The multilayer ceramic capacitor according to  claim 1 , wherein each of the plurality of dielectric layers includes BaTiO 3 , CaTiO 3 , SrTiO 3 , or CaZrO 3  as a main component. 
     
     
         16 . The multilayer ceramic capacitor according to  claim 15 , wherein each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as a additive. 
     
     
         17 . The multilayer ceramic capacitor according to  claim 1 , wherein a distance between each of the plurality of internal electrode layers and each of the first and second side surface is not less than about 0.8 mm and not greater than about 3.0 mm. 
     
     
         18 . The multilayer ceramic capacitor according to  claim 1 , wherein the first external electrode includes an underlying electrode layer and a plated layer covering the underlying electrode layer. 
     
     
         19 . The multilayer ceramic capacitor according to  claim 18 , wherein the underlying electrode layer includes at least one of a baked layer, a resin layer, or a thin-film layer. 
     
     
         20 . The multilayer ceramic capacitor according to  claim 18 , wherein the plated layer includes Ni, Cu, Ag, Pd, or Au or an alloy including at least one of Ni, Cu, Ag, Pd, or Au.

Join the waitlist — get patent alerts

Track US2025336609A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.