Semiconductor Device Fabrication Methods And Structures Thereof

Abstract

A semiconductor structure including a semiconductor channel member, a first dielectric layer over the semiconductor channel member, a second dielectric layer over the first dielectric layer, a metal layer over the second dielectric layer, first dipole elements distributed between the semiconductor channel member and the first dielectric layer, and second dipole elements distributed in the second dielectric layer.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a semiconductor channel member;   a first dielectric layer over the semiconductor channel member;   a second dielectric layer over the first dielectric layer;   a metal layer over the second dielectric layer;   first dipole elements distributed between the semiconductor channel member and the first dielectric layer; and   second dipole elements distributed in the second dielectric layer.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first dipole elements and the second dipole elements have opposite polarities. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein the first dipole elements are of p-type and the second dipole elements are of n-type. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the second dipole elements are distributed in a region of the second dielectric layer,
 wherein the region is adjacent to an interface between the first dielectric layer and the second dielectric layer and is spaced apart from the metal layer.   
     
     
         5 . The semiconductor structure of  claim 1 , wherein the first dipole elements are distributed in a first region and the second dipole elements are distributed in a second region,
 wherein the first region and the second region are separated by a distance in a range of about 5 Å to 30 Å.   
     
     
         6 . The semiconductor structure of  claim 1 , wherein the second dipole elements are further distributed in the first dielectric layer. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the semiconductor channel member is a first semiconductor channel member;
 wherein the semiconductor structure further comprises:
 a second semiconductor channel member above the first semiconductor channel member, 
 a third dielectric layer over the second semiconductor channel member, and 
 a fourth dielectric layer over the third dielectric layer; 
   wherein the first dipole elements are further distributed between the second semiconductor channel member and the third dielectric layer; and   wherein the second dipole elements are further distributed in the fourth dielectric layer.   
     
     
         8 . The semiconductor structure of  claim 7 , wherein the metal layer is further disposed over the fourth dielectric layer. 
     
     
         9 . The semiconductor structure of  claim 7 , wherein the metal layer expands between the second dielectric layer and the fourth dielectric layer. 
     
     
         10 . A semiconductor structure, comprising:
 a semiconductor channel layer;   an interfacial layer over the semiconductor channel layer;   a gate dielectric layer over the interfacial layer;   a work function metal layer over the gate dielectric layer; and   a dipole material distributed in an outer portion of the semiconductor channel layer and an inner portion of the interfacial layer.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the dipole material is a first dipole material,
 wherein the semiconductor structure further comprises a second dipole material distributed in the gate dielectric layer.   
     
     
         12 . The semiconductor structure of  claim 11 , wherein the first dipole material and the second dipole material are of opposite polarities. 
     
     
         13 . The semiconductor structure of  claim 11 , wherein the second dipole material is further distributed in the interfacial layer. 
     
     
         14 . The semiconductor structure of  claim 10 , wherein the dipole material is distributed in a region,
 wherein the region has a thickness of about 1 Å to 15 Å.   
     
     
         15 . A semiconductor structure, comprising:
 a first region comprising a first semiconductor channel member;   a second region comprising a second semiconductor channel member;   an interfacial layer over the first semiconductor channel member and the second semiconductor channel member;   first dipole elements at an interface of the second semiconductor channel member and the interfacial layer;   a gate dielectric layer over the interfacial layer in the first region and the second region;   second dipole elements in the gate dielectric layer in the first region and the second region; and   a metal layer over the gate dielectric layer.   
     
     
         16 . The semiconductor structure of  claim 15 , wherein the first dipole elements are not at an interface of the first semiconductor channel member and the interfacial layer. 
     
     
         17 . The semiconductor structure of  claim 15 , further comprising a third region comprising a third semiconductor channel member,
 wherein the interfacial layer is further over the third semiconductor channel member,   wherein the first dipole elements are further at an interface of the third semiconductor channel member and the interfacial layer,   wherein the gate dielectric layer is further over the interfacial layer in the third region,   wherein the second dipole elements are further in the gate dielectric layer in the third region.   
     
     
         18 . The semiconductor structure of  claim 17 , wherein incorporations of the second dipole elements in the gate dielectric layer in the second region and in the third region are different. 
     
     
         19 . The semiconductor structure of  claim 15 , wherein the second dipole elements are further in the interfacial layer in the first region and the second region. 
     
     
         20 . The semiconductor structure of  claim 15 , further comprising a third region comprising a third semiconductor channel member,
 wherein the interfacial layer is further over the third semiconductor channel member,   wherein the gate dielectric layer is further over the interfacial layer in the third region,   wherein the first dipole elements are not at an interface of the third semiconductor channel member and the interfacial layer,   wherein the second dipole elements are further in the gate dielectric layer in the third region.