Method of making semiconductor device including metal insulator metal capacitor

Abstract

A semiconductor device includes a circuit layer over a first portion of a substrate, wherein the circuit layer exposes a second portion of the substrate. The semiconductor device includes a test line electrically connected to the circuit layer. The semiconductor device includes a capacitor entirely over the second portion of the substrate. In some embodiments, a top surface of the test line is substantially coplanar with a top surface of the capacitor.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a circuit layer over a first portion of a substrate, wherein the circuit layer exposes a second portion of the substrate;   a test line electrically connected to the circuit layer; and   a capacitor entirely over the second portion of the substrate.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a top surface of the test line is substantially coplanar with a top surface of the capacitor. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a conductive layer of the capacitor lands on the second portion of the substrate. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the circuit layer is configured to use the capacitor. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the circuit layer comprises a memory. 
     
     
         6 . The semiconductor device of  claim 1 , wherein a material of the test line is a same material as a conductive layer in the capacitor. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the capacitor comprises a first conductive layer and a second conductive layer, and the first conductive layer is parallel to the second conductive layer. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the test line is at least partially angled with respect to the first conductive layer. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising an insulating layer over the circuit layer. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the test line extends through the insulating layer. 
     
     
         11 . A semiconductor device comprising:
 a circuit layer over a first portion of a substrate, wherein the circuit layer exposes a second portion of the substrate;   a serpentine-shaped test line over the circuit layer;   a via electrically connecting the serpentine-shaped test line to the circuit layer; and   a capacitor landing on the second portion of the substrate.   
     
     
         12 . The semiconductor device of  claim 11 , further comprising an insulator over the substrate. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the capacitor extends through an entirety of the insulator. 
     
     
         14 . The semiconductor device of  claim 12 , wherein the serpentine-shaped test line extends through the insulator. 
     
     
         15 . The semiconductor device of  claim 12 , wherein the insulator contacts a sidewall of the circuit layer. 
     
     
         16 . A method of making a semiconductor device, the method comprising:
 forming a circuit layer over a substrate;   depositing an insulator over the substrate;   patterning the insulator to define a test line trench, a via opening, a first trench, and a second trench, wherein the first trench exposes a portion of the substrate exposed by the circuit layer;   filling the test line trench to define a test line;   filling the via opening to electrically connect the test line to the circuit layer; and   filling the first trench and the second trench to define a capacitor.   
     
     
         17 . The method of  claim 16 , wherein filling the test line trench comprises filling the test line trench simultaneously with filling the first trench. 
     
     
         18 . The method of  claim 16 , further comprising performing a planarization to define a top surface of the test line substantially coplanar with a top surface of the capacitor. 
     
     
         19 . The method of  claim 16 , wherein patterning the insulator comprises defining the test line trench having a serpentine shape. 
     
     
         20 . The method of  claim 16 , wherein forming the circuit layer comprises forming a memory.