SRAM Design with Four-Poly-Pitch

Abstract

A memory cell includes first through fifth gate structures that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively. In some embodiments, the second lateral direction perpendicular to the first lateral direction.

What is claimed is: 
     
         1 . A memory cell, comprising:
 a first active structure, a second active structure, and a third active structure extending along a first lateral direction; and   a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, a fifth gate structure, and a sixth gate structure, each of the first to sixth gate structures extending along a second lateral direction perpendicular to the first lateral direction;   wherein the first and second gate structures are spaced from each other in the second lateral direction and the fifth and sixth gate structures are spaced from each other in the second lateral direction, while the first, second, fifth, and sixth gate structures are in parallel with the third and fourth gate structures;   wherein the first to third active structures and the first to sixth gate structures collectively form a memory cell.   
     
     
         2 . The memory cell of  claim 1 , wherein the memory cell is operatively configured as a Static Random Access Memory (SRAM) cell. 
     
     
         3 . The memory cell of  claim 1 , wherein the memory cell is operatively configured as a ten-transistor Static Random Access Memory (SRAM) cell. 
     
     
         4 . The memory cell of  claim 1 , wherein the first to third active structures are spaced apart from one another along the second lateral direction. 
     
     
         5 . The memory cell of  claim 1 , wherein the first gate structure overlays the first and second active structures, and the second gate structure overlays the third active structure. 
     
     
         6 . The memory cell of  claim 5 , wherein the fifth gate structure overlays the first and second active structures, and the sixth gate structure overlays the third active structure. 
     
     
         7 . The memory cell of  claim 6 , wherein the third and fourth gate structures each overlay all the first to third active structures. 
     
     
         8 . The memory cell of  claim 6 , wherein the first and second gate structures are aligned along the second lateral direction, and the fifth and sixth gate structures are aligned along the second lateral direction. 
     
     
         9 . The memory cell of  claim 1 , wherein the first active structure has p-type, and the second and third active structures each have n-type. 
     
     
         10 . A memory cell, comprising:
 a first active structure, a second active structure, and a third active structure, each of the first to third active structures extending along a first lateral direction; and   a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, a fifth gate structure, and a sixth gate structure, each of the first to sixth gate structures extending along a second lateral direction perpendicular to the first lateral direction;   wherein the first and second gate structures are spaced from but aligned with each other in the second lateral direction, wherein the fifth and sixth gate structures are spaced from but aligned with each other in the second lateral direction, wherein the third and fourth gate structures are interposed between a combination of the first and second gate structures and a combination of the fifth and sixth gate structures along the first lateral direction, and wherein the first, second, fifth, and sixth gate structures are in parallel with the third and fourth gate structures.   
     
     
         11 . The memory cell of  claim 10 , wherein the first to third active structures and the first to sixth gate structures collectively form a memory cell. 
     
     
         12 . The memory cell of  claim 11 , wherein the memory cell is operatively configured as a ten-transistor Static Random Access Memory (SRAM) cell. 
     
     
         13 . The memory cell of  claim 12 , wherein the first active structure and the third to fourth gate structures form a first transistor and a second transistor, wherein the second active structure and the first, third, fourth, and fifth gate structures form a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, and wherein the third active structure and the second, third, fourth, and sixth gate structures form a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. 
     
     
         14 . The memory cell of  claim 10 , wherein the first gate structure overlays the first and second active structures, and the second gate structure also overlays the third active structure. 
     
     
         15 . The memory cell of  claim 14 , wherein the fifth gate structure overlays the first and second active structures, and the sixth gate structure also overlays the third active structure. 
     
     
         16 . The memory cell of  claim 15 , wherein the third gate structure overlays the first to third active structures, and the fourth gate structure overlays the first to third active structures. 
     
     
         17 . The memory cell of  claim 10 , wherein the first active structure has p-type, and the second and third active structures each have n-type. 
     
     
         18 . A memory device, comprising:
 a first active structure, a second active structure, and a third active structure, each of the first to third active structures extending along a first lateral direction; and   a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, a fifth gate structure, and a sixth gate structure, each of the first to sixth gate structures extending along a second lateral direction perpendicular to the first lateral direction;   wherein the first and second gate structures are spaced from but aligned with each other in the second lateral direction, wherein the fifth and sixth gate structures are spaced from but aligned with each other in the second lateral direction, wherein the third and fourth gate structures are interposed between a combination of the first and second gate structures and a combination of the fifth and sixth gate structures along the first lateral direction, and wherein the first, second, fifth, and sixth gate structures are in parallel with the third and fourth gate structures; and   wherein the first to third active structures and the first to sixth gate structures collectively form a memory cell.   
     
     
         19 . The memory device of  claim 18 , wherein the memory cell is operatively configured as a ten-transistor Static Random Access Memory (SRAM) cell. 
     
     
         20 . The memory device of  claim 18 , wherein the first active structure and the third to fourth gate structures form a first transistor and a second transistor, wherein the second active structure and the first, third, fourth, and fifth gate structures form a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, and wherein the third active structure and the second, third, fourth, and sixth gate structures form a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor.