Semiconductor integrated circuit device

Abstract

In a semiconductor integrated circuit device, a plurality of cell rows each including standard cells arranged in the X direction are placed. The plurality of cell rows include a first cell row having a height H 1 and a second cell row having a height H 2 (H 1 <H 2 ). The first cell row includes a logic cell and a cell having no logical function, and the second cell row includes a logic cell and a cell having no logical function. Nanosheets of the cells in the first cell row are smaller in width in the Y direction than nanosheets of the cells in the second cell row.

1 . A semiconductor integrated circuit device, comprising:
 a first cell row including a plurality of standard cells arranged in a first direction; and   a second cell row including a plurality of standard cells arranged in the first direction,   
       wherein
 the first cell row includes
 a first standard cell including a first nanosheet extending in the first direction, the first standard cell having a logical function, and 
 a second standard cell adjacent to the first standard cell, including a second nanosheet extending in the first direction, the second standard cell having no logical function, 
 
 the first nanosheet and the second nanosheet are the same in width and position in a second direction perpendicular to the first direction, 
 the second cell row includes
 a third standard cell including a third nanosheet extending in the first direction, the third standard cell having a logical function, and 
 a fourth standard cell adjacent to the third standard cell, including a fourth nanosheet extending in the first direction, the fourth standard cell having no logical function, 
 
 the third nanosheet and the fourth nanosheet are the same in width and position in the second direction, 
 the first cell row includes
 a first power line formed on a back side of a transistor of the first standard cell, extending in the first direction, having overlaps with the first and second nanosheets in planar view, and supplying a first power supply voltage, 
 
 the second cell row includes
 a second power line formed in a same interconnect layer as the first power line, extending in the first direction, having overlaps with the third and fourth nanosheets in planar view, and supplying the first power supply voltage, and 
 
 the third and fourth nanosheets are greater in width in the second direction than the first and second nanosheets. 
 
     
     
         2 . The semiconductor integrated circuit device of  claim 1 , wherein
 the second power line is greater in width in the second direction than the first power line.   
     
     
         3 . The semiconductor integrated circuit device of  claim 1 , wherein
 at least one of the second and fourth standard cells is a terminal cell.   
     
     
         4 . The semiconductor integrated circuit device of  claim 1 , wherein
 at least one of the second and fourth standard cells is a filler cell.   
     
     
         5 . The semiconductor integrated circuit device of  claim 1 , wherein
 the first and second power lines are formed in an interconnect layer provided in a first semiconductor chip in which the first, second, third, and fourth nanosheets are formed.   
     
     
         6 . The semiconductor integrated circuit device of  claim 1 , wherein
 the first and second power lines are formed in an interconnect layer provided in a second semiconductor chip bonded to a back of a first semiconductor chip in which the first, second, third, and fourth nanosheets are formed.   
     
     
         7 . A semiconductor integrated circuit device, comprising
 a plurality of cell rows each including a plurality of standard cells arranged in a first direction,   
       wherein
 the plurality of cell rows include
 a first cell row including a first standard cell having a first nanosheet extending in the first direction, the first standard cell having a logical function, 
 a second cell row adjacent to the first cell row in a second direction perpendicular to the first direction, having a height different from a height of the first cell row, and including a second standard cell having a second nanosheet extending in the first direction, and 
 a third cell row located on an end of the plurality of cell rows in the second direction, adjoining the first cell row on the side opposite to the second cell row, and including a third standard cell having a third nanosheet extending in the first direction, the third standard cell having no logical function, 
 
 the first cell row includes
 a first power line formed on a back side of a transistor of the first standard cell, extending in the first direction, having an overlap with the first nanosheet in planar view, and supplying a first power supply voltage, 
 
 the second cell row includes
 a second power line formed in a same interconnect layer as the first power line, extending in the first direction, having an overlap with the second nanosheet in planar view, and supplying the first power supply voltage, and 
 
 the third cell row includes
 a third power line formed in a same interconnect layer as the first and second power lines, extending in the first direction, having an overlap with the third nanosheet in planar view, and supplying the first power supply voltage, 
 
 the first nanosheet and the second nanosheet are different in width in the second direction, and 
 the third nanosheet and the second nanosheet are the same in width in the second direction. 
 
     
     
         8 . The semiconductor integrated circuit device of  claim 7 , wherein
 the second power line is different in width in the second direction from the first power line.   
     
     
         9 . The semiconductor integrated circuit device of  claim 7 , wherein
 the third standard cell is smaller in size in the second direction than the second standard cell.   
     
     
         10 . The semiconductor integrated circuit device of  claim 7 , wherein
 the third standard cell includes only either one of a p-type transistor and an n-type transistor.   
     
     
         11 . The semiconductor integrated circuit device of  claim 7 , wherein
 the first, second, and third power lines are formed in an interconnect layer provided in a first semiconductor chip in which the first, second, and third nanosheets are formed.   
     
     
         12 . The semiconductor integrated circuit device of  claim 7 , wherein
 the first, second, and third power lines are formed in an interconnect layer provided in a second semiconductor chip bonded to a back of a first semiconductor chip in which the first, second, and third nanosheets are formed.