Barrier layer on a piezoelectric-device pad

Abstract

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a pad barrier layer caps a pad of a piezoelectric device. The pad barrier layer is configured to block hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer. Absent the pad barrier layer, hydrogen ions from hydrogen-ion containing processes performed after forming the pad may diffuse to the piezoelectric layer along a via extending from the pad to the piezoelectric device. By blocking diffusion of hydrogen ions and/or other errant materials to the piezoelectric device, the pad barrier layer may prevent delamination and breakdown of the piezoelectric layer. Hence, the pad barrier layer may prevent failure of the piezoelectric device.

What is claimed is: 
     
         1 . An integrated circuit (IC) chip, comprising:
 a piezoelectric device overlying a substrate;   a first pad overlying the piezoelectric device;   a first via extending from the first pad to the piezoelectric device;   a second pad overlying the piezoelectric device;   a second via extending from the second pad to the piezoelectric device; and   a barrier layer overlying the first pad and the second pad, wherein the barrier layer is configured to block hydrogen ions from diffusing through the barrier layer, from over the barrier layer to the piezoelectric device.   
     
     
         2 . The IC chip according to  claim 1 , further comprising:
 an additional barrier layer between the first pad and the piezoelectric device, wherein the first via extends through the additional barrier layer, and wherein the additional barrier layer is configured to block hydrogen ions from diffusing through the additional barrier layer, from over the additional barrier layer to the piezoelectric device.   
     
     
         3 . The IC chip according to  claim 1 , further comprising:
 a getter layer underlying and directly contacting the piezoelectric device, wherein the getter layer has a width greater than a width of the piezoelectric device and is configured to getter hydrogen ions.   
     
     
         4 . The IC chip according to  claim 3 , wherein the getter layer consists essentially of a metal element, wherein the barrier layer comprises a metal oxide, and wherein the metal oxide comprises a metal element different than the metal element of the getter layer. 
     
     
         5 . The IC chip according to  claim 1 , wherein the substrate comprises a moveable membrane at an opening extending through the substrate, and wherein the piezoelectric device extends in a closed path around the moveable membrane. 
     
     
         6 . The IC chip according to  claim 5 , wherein the barrier layer is on a sidewall of the moveable membrane. 
     
     
         7 . The IC chip according to  claim 5 , further comprising:
 a passivation layer overlying the barrier layer, wherein the passivation layer is on a sidewall of the moveable membrane, and wherein the barrier layer is spaced from the moveable membrane.   
     
     
         8 . An integrated circuit (IC) chip, comprising:
 a piezoelectric device overlying a substrate, wherein the piezoelectric device comprises a bottom electrode, a piezoelectric layer overlying the bottom electrode, and a top electrode overlying the piezoelectric layer;   a pad overlying and spaced from the piezoelectric device;   a via extending from the pad to the bottom or top electrode of the piezoelectric device; and   a barrier layer overlying the pad, wherein the barrier layer is configured to block hydrogen ions from diffusing through the barrier layer, from over the barrier layer to the piezoelectric device.   
     
     
         9 . The IC chip according to  claim 8 , wherein an entirety of the via directly overlies the piezoelectric device. 
     
     
         10 . The IC chip according to  claim 8 , wherein the barrier layer extends along individual sidewalls respectively of the bottom electrode, the top electrode, and the piezoelectric layer. 
     
     
         11 . The IC chip according to  claim 8 , wherein the pad has a first end directly over and electrically coupled to the piezoelectric device by the via, and wherein the pad further has a second end that is distal from the first end and laterally offset from the piezoelectric device. 
     
     
         12 . The IC chip according to  claim 8 , wherein the piezoelectric device has a ring-shaped top geometry that surrounds an opening extending through the substrate. 
     
     
         13 . The IC chip according to  claim 12 , wherein the substrate comprises a lower semiconductor layer, an insulator layer overlying the lower semiconductor layer, and an upper semiconductor layer overlying the insulator layer, and wherein the substrate comprises a moveable membrane localized to the upper semiconductor layer and overlying the opening. 
     
     
         14 . The IC chip according to  claim 8 , wherein the pad and the via comprise aluminum, and wherein the barrier layer comprises aluminum oxide. 
     
     
         15 . A method, comprising:
 forming a piezoelectric structure over a substrate, wherein the piezoelectric structure extends laterally in a closed path around a central area of the substrate;   forming a pad having a first end overlying and electrically coupled to a top of the piezoelectric structure and a second end, opposite the first end, laterally offset from the piezoelectric structure;   depositing a hydrogen-barrier layer covering the pad and the piezoelectric structure;   performing a first etch into the central area of the substrate to form a membrane;   performing a second etch into the hydrogen-barrier layer to form a pad opening exposing the second end of the pad; and   releasing the membrane to allow movement of the membrane.   
     
     
         16 . The method according to  claim 15 , wherein the first etch exposes the hydrogen-barrier layer to hydrogen ions. 
     
     
         17 . The method according to  claim 15 , further comprising:
 depositing a passivation layer covering the hydrogen-barrier layer, wherein the second etch is further performed into the passivation layer, and wherein the depositing of the passivation layer and/or the second etch expose the hydrogen-barrier layer to hydrogen ions.   
     
     
         18 . The method according to  claim 15 , wherein the substrate comprises a backside semiconductor layer, an insulator layer overlying the backside semiconductor layer, and a frontside semiconductor layer overlying the insulator layer, wherein the first etch forms a plurality of slits extending through the frontside semiconductor layer to the insulator layer, and wherein the plurality of slits are spaced from the backside semiconductor layer by the insulator layer and demarcate the membrane. 
     
     
         19 . The method according to  claim 18 , further comprising:
 depositing a sacrificial material filling the plurality of slits and covering the membrane; and   performing a third etch into the backside semiconductor layer and the insulator layer to expose the plurality of slits and the membrane, wherein the releasing comprises removing the sacrificial material after the third etch.   
     
     
         20 . The method according to  claim 15 , further comprising:
 depositing a hydrogen getter layer overlying the substrate, wherein the piezoelectric structure is formed overlying and directly contacting the hydrogen getter layer.