Testing structure for an integrated chip having a high-voltage device

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first deep trench isolation (DTI) structure in a substrate. A dielectric structure is over the substrate. An interconnect structure is in the dielectric structure. The interconnect structure includes a lower interconnect structure and an upper interconnect structure that are electrically coupled together. The upper interconnect structure includes a plurality of conductive plates. The plurality of conductive plates are vertically stacked and electrically coupled together. A back-side through substrate via (BTSV) is in the substrate and the dielectric structure. The BTSV extends from a conductive feature of the lower interconnect structure through the dielectric structure and the substrate. The conductive feature of the lower interconnect structure is at least partially laterally within a perimeter of the DTI structure. The BTSV is within the perimeter of the DTI structure.

What is claimed is: 
     
         1 . An integrated chip (IC), comprising:
 a first ring-shaped deep trench isolation (DTI) structure disposed in a semiconductor substrate;   a dielectric structure disposed over the semiconductor substrate;   a conductive interconnect structure disposed in the dielectric structure, wherein:
 the conductive interconnect structure comprises a lower conductive interconnect structure; 
 the conductive interconnect structure comprises an upper conductive interconnect structure disposed over and electrically coupled to the lower conductive interconnect structure; 
 the upper conductive interconnect structure comprises a plurality of conductive plates; and 
 the plurality of conductive plates are vertically stacked and electrically coupled together; and 
   a back-side through substrate via (BTSV) disposed in the semiconductor substrate and the dielectric structure, wherein the BTSV extends from a first conductive feature of the lower conductive interconnect structure through both the dielectric structure and the semiconductor substrate, wherein the first conductive feature of the lower conductive interconnect structure is disposed at least partially laterally within a perimeter of the first ring-shaped DTI structure, and wherein the BTSV is disposed within the perimeter of the first ring-shaped DTI structure.   
     
     
         2 . The IC of  claim 1 , wherein a lowermost surface of the first conductive feature of the lower conductive interconnect structure is vertically spaced from the semiconductor substrate. 
     
     
         3 . The IC of  claim 1 , a shallow trench isolation (STI) structure disposed in the semiconductor substrate, wherein the first ring-shaped DTI structure penetrates the STI structure, and wherein the BTSV extends vertically through the STI structure. 
     
     
         4 . The IC of  claim 1 , wherein:
 the plurality of conductive plates have outer perimeters, respectively; and   each of the outer perimeters have a substantially similar size and shape.   
     
     
         5 . The IC of  claim 1 , wherein:
 each of the plurality of conductive plates comprises a plurality of slats;   the plurality of slates of a first conductive plate of the plurality of conductive plates extend laterally in a first direction;   the plurality of slates of a second conductive plate of the plurality of conductive plates extend laterally in a second direction perpendicular to the first direction; and   the second conductive plate is disposed nearer the first conductive plate than any other conductive plates of the plurality of conductive plates.   
     
     
         6 . The IC of  claim 1 , wherein:
 the lower conductive interconnect structure comprises a plurality of dummy structures disposed within the perimeter of the first ring-shaped DTI structure; and   the plurality of dummy structures are disposed within an array comprising a plurality of rows and a plurality of columns.   
     
     
         7 . The IC of  claim 6 , wherein:
 a first conductive plate of the plurality of conductive plates comprises a first plurality of conductive slats that extend laterally in a first direction; and   the first plurality of conductive slats extend laterally in the first direction between neighboring rows of the plurality of rows.   
     
     
         8 . The IC of  claim 7 , wherein:
 a second conductive plate of the plurality of conductive plates comprises a second plurality of conductive slats that extend laterally in a second direction perpendicular to the first direction; and   the second plurality of conductive slats extend laterally in the second direction between neighboring columns of the plurality of columns.   
     
     
         9 . The IC of  claim 1 , further comprising:
 a second ring-shaped DTI structure disposed in the semiconductor substrate, wherein:
 the second ring-shaped DTI structure is disposed within the perimeter of the first ring-shaped DTI structure; and 
 the BTSV is disposed laterally between the perimeter of the first ring-shaped DTI structure and a perimeter of the second ring-shaped DTI structure. 
   
     
     
         10 . The IC of  claim 9 , further comprising:
 a shallow trench isolation (STI) structure disposed in the semiconductor substrate, wherein the first ring-shaped DTI structure and the second ring-shaped DTI structure both penetrate the STI structure, and wherein the BTSV extends vertically through the STI structure.   
     
     
         11 . The IC of  claim 1 , wherein:
 the lower conductive interconnect structure comprises a second conductive feature different than the first conductive feature;   the first conductive feature and the second conductive feature are both disposed along a plane that extends laterally in parallel with an upper surface of the semiconductor substrate;   a third conductive feature of the lower conductive interconnect structure extends vertically from the semiconductor substrate to the second conductive feature;   the third conductive feature is disposed within the perimeter of the first ring-shaped DTI structure; and   the third conductive feature electrically couples the second conductive feature to a region of the semiconductor substrate that is laterally surrounded by the first ring-shaped DTI structure.   
     
     
         12 . The IC of  claim 11 , further comprising:
 a second ring-shaped DTI structure disposed in the semiconductor substrate, wherein:
 the second ring-shaped DTI structure is disposed within the perimeter of the first ring-shaped DTI structure; 
 the BTSV is disposed laterally between the perimeter of the first ring-shaped DTI structure and a perimeter of the second ring-shaped DTI structure; 
 the third conductive feature is disposed laterally between the perimeter of the first ring-shaped DTI structure and the perimeter of the second ring-shaped DTI structure; and 
 the region of the semiconductor substrate is also disposed laterally between the perimeter of the first ring-shaped DTI structure and the perimeter of the second ring-shaped DTI structure. 
   
     
     
         13 . The IC of  claim 1 , further comprising:
 an input/output (I/O) structure disposed on a first side of the semiconductor substrate, wherein:
 the conductive interconnect structure is disposed on a second side of the semiconductor substrate opposite the first side of the semiconductor substrate; and 
 the BTSV electrically couples the I/O structure to the first conductive feature of the lower conductive interconnect structure. 
   
     
     
         14 . An integrated chip (IC), comprising:
 a dielectric structure disposed on a side of a semiconductor substrate;   a conductive interconnect structure disposed in the dielectric structure, wherein:
 the conductive interconnect structure is disposed in both a device region of the IC and a testing region of the IC; 
 a semiconductor device is disposed on the semiconductor substrate and in the device region of the IC; 
 the testing region of the IC is disposed outside a perimeter of the semiconductor device; 
 the conductive interconnect structure comprises a first lower conductive interconnect structure and a first upper conductive interconnect structure both disposed in the testing region of the IC; 
 the first upper conductive interconnect structure is disposed over and electrically coupled to the first lower conductive interconnect structure; 
 the first upper conductive interconnect structure comprises a plurality of conductive plates; and 
 the plurality of conductive plates are vertically stacked and electrically coupled together; and 
   a plurality of back-side through substrate vias (BTSVs) disposed in the semiconductor substrate and the dielectric structure, wherein the plurality of BTSVs contact a plurality of conductive features of the first lower conductive interconnect structure, respectively, wherein each of the plurality of BTSVs extend from a corresponding one of the plurality of conductive features through both the dielectric structure and the semiconductor substrate, and wherein each of the plurality of BTSVs are disposed within the testing region of the IC.   
     
     
         15 . The IC of  claim 14 , wherein:
 each of the conductive features of the plurality of conductive features are vertically spaced from an upper surface of the semiconductor substrate;   each of the conductive features of the plurality of conductive features are disposed along a plane; and   the plane extends laterally in parallel with an upper surface of the semiconductor substrate.   
     
     
         16 . The IC of  claim 15 , wherein:
 the conductive interconnect structure comprises a second lower conductive interconnect structure and a second upper conductive interconnect structure both disposed in the device region of the IC;   the second lower conductive interconnect structure comprises a conductive wire disposed along the plane;   the second lower conductive interconnect structure comprises one or more conductive contacts that extend vertically from the semiconductor substrate to the conductive wire; and   the one or more conductive contacts electrically couple the semiconductor device to the conductive wire.   
     
     
         17 . The IC of  claim 14 , wherein the semiconductor device is disposed nearer the testing region of the IC than any other semiconductor device of the IC. 
     
     
         18 . The IC of  claim 14 , wherein:
 the plurality of conductive plates comprises a first conductive plate disposed over the first lower conductive interconnect structure; and   each of the plurality of BTSVs are disposed at least partially laterally within an outer perimeter of the first conductive plate.   
     
     
         19 . A method for forming an integrated chip (IC), the method comprising:
 receiving a workpiece comprising:
 an interlayer dielectric (ILD) structure disposed on a first side of a semiconductor substrate; 
 a conductive interconnect structure disposed in the ILD structure, wherein the conductive interconnect structure comprises a plurality of metal layers, wherein a first metal layer of the plurality of metal layers is disposed nearer the semiconductor substrate than each of the other metal layers of the plurality of metal layers, wherein the first metal layer comprises a conductive feature, wherein the conductive interconnect structure further comprises a stack of conductive plates that are electrically coupled together, wherein the stack of conductive plates are electrically coupled to the conductive feature, and wherein the first metal layer vertically separates the stack of conductive plates from the semiconductor substrate; 
 a shallow trench isolation (STI) structure disposed in the semiconductor substrate; and 
 a ring-shaped deep trench isolation (DTI) structure disposed in the semiconductor substrate, wherein the ring-shaped DTI structure penetrates the STI structure, wherein the stack of conductive plates are disposed at least partially laterally within a perimeter of the ring-shaped DTI structure, and wherein the conductive feature is disposed at least partially laterally within a perimeter of the ring-shaped DTI structure; and 
   forming a first dielectric structure on a second side of the semiconductor substrate opposite the first side of the semiconductor substrate;   forming an initial trench penetrating the first dielectric structure and the semiconductor substrate, wherein the initial trench is formed laterally within the perimeter of the ring-shaped DTI structure, and wherein a surface of the STI structure defines a surface of the initial trench;   forming a second dielectric structure along sidewalls of the initial trench and along the surface of the initial trench;   extending the initial trench to the conductive feature, thereby forming a back-side through substrate via (BTSV) trench that exposes the conductive feature, wherein extending the initial trench comprises penetrating the second dielectric structure, the STI structure, and the ILD structure; and   forming a BTSV in the BTSV trench, wherein the BTSV is electrically coupled to the conductive feature.   
     
     
         20 . The method of  claim 19 , further comprising:
 after the BTSV is formed, forming a passivation structure on a side of the first dielectric structure, wherein the first dielectric structure is disposed vertically between the passivation structure and the semiconductor substrate;   forming an opening in the passivation structure that exposes the BTSV;   forming a conductive via in the opening and electrically coupled to the BTSV; and   forming an input/output (I/O) structure on the conductive via, wherein the I/O structure is electrically coupled to the conductive via, and wherein both the conductive via and the passivation structure are disposed vertically between the I/O structure and the BTSV.