Display substrate and manufacturing method therefor, and display device

Abstract

Provided is a display substrate, including a capacitance compensation region which is provided with a first capacitance compensation unit. The first capacitance compensation unit includes a semiconductor structure, a first metal structure, and a second metal structure sequentially arranged on a base substrate. An insulation layer between the semiconductor structure and the second metal structure is provided with a plurality of first via holes that are arranged along a first direction, and the second metal structure is connected to the semiconductor structure by means of the plurality of first via holes. The first metal structure includes a plurality of second gate lines extending along the first direction. In a second direction perpendicular to the first direction, a distance between two adjacent first via holes is at least greater than a sum of widths of two second gate lines.

1 . A display substrate, comprising:
 a display region, a notch region, and a capacitance compensation region, wherein:   the display region at least partially surrounds the notch region, and the capacitance compensation region is located between the display region and the notch region; a plurality of first gate lines is provided in the display region;   a first capacitance compensation unit is provided in the capacitance compensation region;   the first capacitance compensation unit comprises a semiconductor structure, a first metal structure, and a second metal structure disposed on a base substrate sequentially; the semiconductor structure and the first metal structure are insulated from each other, and the first metal structure and the second metal structure are insulated from each other; a plurality of first vias are provided in an insulation layer between the semiconductor structure and the second metal structure, and the second metal structure is connected with the semiconductor structure through the plurality of first vias;   the first metal structure comprises a plurality of second gate lines extending along a first direction, and at least one of the second gate lines is connected with a corresponding first gate line; an orthographic projection of a second gate line on the base substrate is at least partially overlapped with an orthographic projection of the second metal structure on the base substrate, and the orthographic projection of the second gate line on the base substrate is at least partially overlapped with an orthographic projection of the semiconductor structure on the base substrate; the second gate line forms a capacitor together with the second metal structure and the semiconductor structure;   the semiconductor structure comprises at least one semiconductor block, the plurality of first vias are respectively located on an edge of one side or on edges of both sides, which are opposite to each other, of the at least one semiconductor block in a second direction;   the at least one semiconductor block comprises a plurality of semiconductor blocks arranged along the first direction sequentially; and   the plurality of semiconductor blocks comprises first blocks and second blocks, the first blocks are arranged at both ends of the second blocks along the first direction, lengths of first blocks located at an edge of the semiconductor structure increase first and then decrease in the first direction.   
     
     
         2 . The display substrate according to  claim 1 , wherein the plurality of first vias are arranged along the first direction, and in the second direction perpendicular to the first direction, a distance between two adjacent first vias of the plurality of first vias is at least greater than a sum of widths of two second gate lines of the plurality of second gate lines. 
     
     
         3 . The display substrate according to  claim 1 , wherein the first metal structure comprises N second gate lines extending along the first direction; and
 in the second direction perpendicular to the first direction, the distance between the two adjacent first vias is at least greater than the sum of the widths of the two second gate lines and less than a sum of widths of the N second gate lines, wherein N is an integer greater than 4.   
     
     
         4 . The display substrate according to  claim 1 , wherein the first metal structure comprises N second gate lines extending along the first direction, N being an integer greater than 1; and
 in the second direction perpendicular to the first direction, the distance between the two adjacent first vias is greater than a sum of widths of the N second gate lines.   
     
     
         5 . The display substrate according to  claim 1 , wherein a length of at least one semiconductor block along the first direction is within 10 microns to 300 microns. 
     
     
         6 . The display substrate according to  claim 1 , wherein the orthographic projection of the second metal structure on the base substrate covers the orthographic projection of the semiconductor structure on the base substrate. 
     
     
         7 . The display substrate according to  claim 1 , wherein a width of at least one second gate line comprised in the first metal structure is different from a width of an adjacent second gate line. 
     
     
         8 . The display substrate according to  claim 1 , wherein the capacitance compensation region is further provided with a second capacitance compensation unit, the second capacitance compensation unit comprises a third metal structure and a fourth metal layer structure that are disposed on the base substrate sequentially and insulated from each other; the third metal structure and the first metal structure are structures on a same layer, and the fourth metal structure and the second metal structure are structures on a same layer; an orthographic projection of the third metal structure on the base substrate is at least partially overlapped with an orthographic projection of the fourth metal structure on the base substrate, and the third metal structure and the fourth metal structure form a capacitor. 
     
     
         9 . The display substrate according to  claim 8 , wherein the display region comprises a first sub-display region and a second sub-display region, the first sub-display region and the second sub-display region are located respectively on both sides of the notch region which are opposite to each other, in the capacitance compensation region, the second capacitance compensation unit is located on one side of the first capacitance compensation unit close to the first sub-display region or on one side of the first capacitance compensation unit close to the second sub-display region. 
     
     
         10 . The display substrate according to  claim 8 , wherein each of the plurality of second gate lines comprises two curve segments and one straight line segment; both ends of the straight line segment of at least one of the second gate lines are respectively connected with one curve segment of the two curve segments, one of the curve segments is connected with a first gate line in the first sub-display region, and the other of the curve segments is connected with a first gate line in the second sub-display region. 
     
     
         11 . The display substrate according to  claim 10 , wherein the second metal structure at least comprises a first potential signal line extending along the first direction; a width of the first potential signal line is greater than a width of the second gate line; an orthographic projection of the curve segment of the second gate line close to the notch region on the base substrate is covered by an orthographic projection of the first potential signal line on the base substrate; the second gate line is overlapped with the first potential signal line to form a capacitor; and the capacitor is used as the second capacitance compensation unit to increase a loading capacitance on the first gate line. 
     
     
         12 . The display substrate according to  claim 1 , wherein, the second metal structure at least comprises a first potential signal line extending along the first direction. 
     
     
         13 . The display substrate according to  claim 12 , further comprising a border region located at a periphery of the display region and away from the notch region; wherein a width of a first potential signal line in the capacitance compensation region is greater than a width of a first potential signal line in the border region. 
     
     
         14 . The display substrate according to  claim 12 , wherein the first potential signal line in the capacitance compensation region has a main body portion and an extension portion; the main body portion extends along the first direction, the extension portion extends along the second direction, and one end of the extension portion close to the notch region is connected with the main body portion; a length of the extension portion in the first direction increases gradually and then decreases along a direction away from the notch region. 
     
     
         15 . The display substrate according to  claim 12 , wherein the second metal structure further comprises an extension electrode, and the extension electrode is connected with the first potential signal line through a plurality of connection electrodes. 
     
     
         16 . The display substrate according to  claim 15 , wherein a plurality of second vias are provided in an insulation layer between a film layer where the plurality of connection electrodes are located and the second metal structure, and the extension electrode and the first potential signal line are respectively connected with the connection electrodes through the plurality of second vias;
 the first vias and the second vias are spaced apart from each other and arranged along the first direction.   
     
     
         17 . The display substrate according to  claim 12 , wherein the first potential signal line is a low potential power line or a high potential power line. 
     
     
         18 . The display substrate according to  claim 1 , wherein a plurality of sub-pixels arranged regularly are provided in the display region, at least one sub-pixel comprises a light emitting element and a drive circuit for driving the light emitting element to emit light, and the drive circuit comprises a plurality of transistors and a storage capacitor;
 the display region comprises a base substrate, and a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer which are disposed on the base substrate sequentially;   the semiconductor layer comprises active layers of the plurality of transistors;   the first conductive layer comprises gate electrodes of the plurality of transistors, a first electrode of the storage capacitor, and a first gate line connected with a gate electrode;   the second conductive layer comprises a second electrode of the storage capacitor;   the third conductive layer comprises source electrodes and drain electrodes of the plurality of transistors;   the semiconductor structure is disposed on a same layer as the semiconductor layer, and the first metal structure is disposed on a same layer as the second conductive layer; the second metal structure is disposed on a same layer as the third conductive layer;   a second gate line comprised in the first metal structure is connected with a corresponding first gate line in the first conductive layer.   
     
     
         19 . The display substrate according to  claim 18 , wherein a plurality of second vias are provided in a third insulation layer between a layer where a plurality of connection electrodes are located and the second metal structure, the second metal structure at least comprises a first potential signal line extending along the first direction and an extension electrode, the extension electrode is connected with the first potential signal line through the plurality of connection electrodes; the plurality of connection electrodes is arranged on a same layer as the second gate lines; the extension electrode and the first potential signal line are respectively connected with the plurality of connection electrodes through the second vias provided on the third insulation layer. 
     
     
         20 . A display apparatus, comprising the display substrate according to  claim 1 .