Three-dimensional (3d) package

Abstract

A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

What is claimed is: 
     
         1 . A package comprising:
 an interconnect die free of any active devices;   a passive device die free of any active devices;   a dielectric material surrounding the interconnect die and the passive device die;   first metallization pattern bonded to the interconnect die and the passive device die;   a first underfill between the interconnect die and the first metallization pattern; and   a second underfill between the passive device die and the first metallization pattern, wherein the dielectric material extends continuously from a first sidewall of the first underfill to a second sidewall of the second underfill; and   a first device die bonded to an opposing side of the first metallization pattern as the interconnect die; and   a second device die bonded to a same side of the first metallization pattern as the first device die, wherein the interconnect die overlaps the first device die and the second device die.   
     
     
         2 . The package of  claim 1  further comprising:
 a second metallization pattern on an opposing side of the dielectric material as the first metallization pattern. 
 
     
     
         3 . The package of  claim 2  further comprising through vias extending through the dielectric material, wherein the through vias electrically connect the first metallization pattern to the second metallization pattern. 
     
     
         4 . The package of  claim 2  further comprising:
 a core substrate bonded to an opposing surface of the second metallization pattern as the dielectric material. 
 
     
     
         5 . The package of  claim 1 , wherein the interconnect die is bonded to the first metallization pattern by a plurality of first connectors, wherein the passive device die is bonded to the first metallization pattern by a plurality of second connectors, and wherein the plurality of first connectors have a same configuration as the plurality of second connectors. 
     
     
         6 . The package of  claim 1 , wherein the interconnect die is bonded to the first metallization pattern by a plurality of first connectors, wherein the passive device die is bonded to the first metallization pattern by a plurality of second connectors, and wherein the plurality of first connectors have a different configuration than the plurality of second connectors. 
     
     
         7 . The package of  claim 1 , wherein the first underfill contacts first sidewalls of a first conductive feature of the first metallization pattern, and wherein the second underfill contacts second sidewalls of a second conductive feature of the first metallization pattern. 
     
     
         8 . A semiconductor assembly comprising:
 a transistor-free interposer component including:
 an interconnect die and a passive device die; 
 a dielectric material enveloping the interconnect die and the passive device die;
 conductive vias extending through the dielectric material; 
 
 a first metallization layer interfacing the interconnect die, the passive device die, and the conductive vias; 
 a first underfill between the interconnect die and the first metallization layer; and 
 a second underfill between the passive device die and the first metallization layer, wherein the dielectric material separates the first underfill and the second underfill; 
   a first functional die coupled to a reverse surface of the first metallization layer opposite from the interconnect die; and   a second functional die mounted to the reverse surface of the first metallization layer, wherein the interconnect die includes one or more electrical communication pathways between the first functional die and the second functional die.   
     
     
         9 . The semiconductor assembly of  claim 8 , wherein the transistor-free interposer component further comprises a second metallization layer, the dielectric material is interposed between the first metallization layer and the second metallization layer, and the conductive vias electrically connects the first metallization layer to the second metallization layer. 
     
     
         10 . The semiconductor assembly of  claim 8 , wherein the interconnect die and the passive device die at disposed between adjacent ones of the conductive vias. 
     
     
         11 . The semiconductor assembly of  claim 8 , wherein the first functional die overlaps the passive device die. 
     
     
         12 . The semiconductor assembly of  claim 8 , wherein first solder connectors of the interconnect die and second solder connectors of the passive device die interface the first metallization layer. 
     
     
         13 . The semiconductor assembly of  claim 12 , wherein the first functional die is bonded to the first metallization layer by third solder connectors, and wherein the second functional die is bonded to the first metallization layer by fourth solder connectors. 
     
     
         14 . The semiconductor assembly of  claim 12 , wherein the dielectric material interfaces sidewalls of the first metallization layer. 
     
     
         15 . A semiconductor device comprising:
 an interconnect device flip chip bonded to a first surface of a first metallization structure by first solder connectors, wherein the interconnect device is free of any transistors;   a passive device flip chip bonded to the first surface of the first metallization structure by second solder connectors, wherein the passive device is free of any transistors;   a first underfill around the first solder connectors;   a second underfill around the second solder connectors, wherein the first underfill and the second underfill are physically separated;   a dielectric film around the interconnect device, the passive device, the first underfill, and the second underfill, wherein the dielectric film is disposed between the first metallization structure and a second metallization structure;   a first device die bonded to a second surface of the first metallization structure, wherein the second surface of the first metallization structure is opposite to the first surface of the first metallization structure; and   a second device die bonded to the second surface of the first metallization structure, wherein the interconnect device is electrically connected to both the first device die and the second device die.   
     
     
         16 . The semiconductor device of  claim 15  further comprising through vias extending through the dielectric film, wherein the through vias electrically connect the first metallization structure to the second metallization structure. 
     
     
         17 . The semiconductor device of  claim 16 , wherein the first device die overlaps a first through via of the through vias, the passive device die, and the interconnect device. 
     
     
         18 . The semiconductor device of  claim 17 , wherein the second device die overlaps a second through via of the through vias and the interconnect device. 
     
     
         19 . The semiconductor device of  claim 15 , further comprising a package substrate bonded to an opposing side of the second metallization structure as the dielectric film. 
     
     
         20 . The semiconductor device of  claim 15 , wherein the dielectric film separates the first underfill from the second underfill.