Semiconductor device and electronic system including the same

Abstract

A semiconductor device may include a semiconductor substrate including a cell array area, an extension area, and a pad area; a first stacked structure on the cell array area and the extension area, the first stacked structure including first conductive layers and first insulating layers alternately stacked; an input/output pad on an upper end portion of the pad area; a second stacked structure on a lower side of the input/output pad and including a plurality of second conductive layers and a plurality of second insulating layers alternately stacked on the pad area; a plurality of through wiring structures respectively connected to the plurality of second conductive layers on the pad area; and a mold insulator between the input/output pad and the second stacked structure such that the input/output pad and the second stacked structure may be vertically spaced apart from each other.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate including a cell array area, an extension area, and a pad area;   a first stacked structure on the cell array area and the extension area, the first stacked structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked;   an input/output pad on an upper end portion of the pad area;   a second stacked structure on a lower side of the input/output pad, the second stacked structure including a plurality of second conductive layers and a plurality of second insulating layers alternately stacked on the pad area;   a plurality of through wiring structures respectively connected to the plurality of second conductive layers on the pad area; and   a mold insulator between the input/output pad and the second stacked structure such that the input/output pad and the second stacked structure are vertically spaced apart from each other.   
     
     
         2 . The semiconductor device of  claim 1 , wherein an upper end of the second stacked structure is lower than an upper end of the first stacked structure. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the second stacked structure and the plurality of through wiring structures are configured to function as at least one of capacitors, resistors, or connection wires. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the plurality of through wiring structures comprise:
 a first through wiring structure connected to a first one of the plurality of second conductive layers; and   a second through wiring structure connected to a second one of the plurality of second conductive layers.   
     
     
         5 . The semiconductor device of  claim 4 , wherein
 a single capacitor includes the first one of the plurality of second conductive layers, the second one of the plurality of second conductive layers, and one of the plurality of second insulating layers therebetween.   
     
     
         6 . The semiconductor device of  claim 4 , wherein
 one or more of the plurality of second conductive layers and two or more of the plurality of second insulating layers are between the first one of the plurality of second conductive layers and the second one of the plurality of second conductive layers,   the one or more of the plurality of second conductive layers and the second one of the plurality of second conductive layers are configured so that electricity does not flow therethrough, and   the first one of the plurality of second conductive layers, the second one of the plurality of second conductive layers, and the one or more of the plurality of the second conductive layers and the two or more second insulating layers are configured to function as a single capacitor.   
     
     
         7 . The semiconductor device of  claim 4 , wherein the first through wiring structure and the second through wiring structure are alternately arranged in a horizontal direction. 
     
     
         8 . The semiconductor device of  claim 3 , wherein the plurality of through wiring structures further comprise:
 a first through wiring structure connected to a first one of the plurality of second conductive layers; and   a second through wiring structure connected to a second one of the plurality of second conductive layers, wherein   the first one of the plurality of second conductive layers is configured to function as a resistor or a connection wire.   
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 a connection structure connected to the input/output pad, wherein   the connection structure is configured for being electrically connected to a package substrate.   
     
     
         10 . The semiconductor device of  claim 1 , wherein the first conductive layers are word lines or bit lines. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the first stacked structure and the second stacked structure are manufactured simultaneously by a same process. 
     
     
         12 . The semiconductor device of  claim 1 , comprising:
 a cell array structure comprising the first stacked structure and the second stacked structure; and   a peripheral circuit structure positioned at a lower end of the cell array structure and electrically connected to the cell array structure through a bonding pad.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the input/output pad is at an upper end of the cell array structure. 
     
     
         14 . The semiconductor device of  claim 13 , further comprising:
 an input/output contact structure penetrating the cell array structure, wherein   the input/output contact structure electrically connects the input/output pad and the peripheral circuit structure.   
     
     
         15 . The semiconductor device of  claim 1 , further comprising:
 a plurality of channel structures penetrating the first stacked structure in the cell array area; and   a plurality of cell contact plugs respectively connected to the plurality of first conductive layers in the extension area.   
     
     
         16 . An electronic system comprising:
 a package substrate;   a semiconductor device on the package substrate; and   a connection structure electrically connecting the package substrate and the semiconductor device, wherein   the semiconductor device includes
 a semiconductor substrate including a cell array area, an extension area, and a pad area, 
 a first stacked structure on the cell array area and the extension area, the first stacked structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked, 
 an input/output pad on an upper end portion of the pad area and electrically connected to the package substrate through the connection structure, 
 a second stacked structure on a lower side of the input/output pad, the second stacked structure including a plurality of second conductive layers and a plurality of second insulating layers alternately stacked, 
 a plurality of through wiring structures respectively connected to the plurality of second conductive layers on the pad area, and 
 a mold insulator between the input/output pad and the second stacked structure such that the input/output pad and the second stacked structure are vertically spaced apart from each other. 
   
     
     
         17 . The electronic system of  claim 16 , wherein an upper end of the second stacked structure is lower than an upper end of the first stacked structure. 
     
     
         18 . The electronic system of  claim 16 , wherein the second stacked structure and the plurality of through wiring structures are configured to function as at least one of capacitors, resistors, or connection wires. 
     
     
         19 . The electronic system of  claim 16 , wherein the first conductive layers are word lines or bit lines. 
     
     
         20 . The electronic system of  claim 16 , wherein the first stacked structure and the second stacked structure are manufactured simultaneously by a same process.