Method and device for quick boot of high bandwidth memory (hbm) dies

Abstract

Methods and devices are provided in which a central processing unit (CPU) of a first chiplet of a superchip may load a first boot code of the first chiplet and a second boot code of a second chiplet of the superchip. The CPU may initialize the first chiplet based on the first boot code. The CPU may initialize the second chiplet based on the second boot code via first configuration instructions sent through a compute die of the superchip.

What is claimed is: 
     
         1 . A method comprising:
 loading, by a central processing unit (CPU) of a first chiplet of a superchip, a first boot code of the first chiplet and a second boot code of a second chiplet of the superchip;   initializing, by the CPU, the first chiplet based on the first boot code; and   initializing, by the CPU, the second chiplet based on the second boot code via first configuration instructions sent through a compute die of the superchip.   
     
     
         2 . The method of  claim 1 , further comprising:
 configuring the first chiplet as a main chiplet of the superchip through embedded fuse programming or hardwiring.   
     
     
         3 . The method of  claim 1 , wherein the first boot code and the second boot code are loaded from an external device via a boot loader module of the first chiplet. 
     
     
         4 . The method of  claim 1 , further comprising:
 performing, by the CPU, a security check to ensure that hardware signatures are acceptable for the first boot code and the second boot code.   
     
     
         5 . The method of  claim 1 , wherein initializing the first chiplet comprises configuring internal components of the first chiplet. 
     
     
         6 . The method of  claim 1 , wherein initializing the second chiplet comprises:
 sending, by the CPU, the first configuration instructions to the second chiplet via an interconnection module of the compute die.   
     
     
         7 . The method of  claim 1 , further comprising:
 loading, by the CPU, a third boot code of a third chiplet of the superchip; and   initializing, by the CPU, the third chiplet based on the third boot code via second configuration instructions sent through the compute die,   wherein the initializing of the second chiplet and the third chiplet are performed in parallel.   
     
     
         8 . A superchip comprising:
 a compute chip;   a first chiplet; and   a second chiplet,   wherein the first chiplet comprises a central processing unit (CPU) configured to:
 load a first boot code of the first chiplet and a second boot code of the second chiplet; 
 initialize the first chiplet based on the first boot code; and 
 initialize the second chiplet based on the second boot code via first configuration instructions sent through the compute die. 
   
     
     
         9 . The superchip of  claim 8 , wherein the CPU is further configured to:
 configure the first chiplet as a main chiplet of the superchip through embedded fuse programming or hardwiring.   
     
     
         10 . The superchip of  claim 8 , wherein the first chiplet further comprises a boot loader module configured to load the first boot code and the second boot code from an external device. 
     
     
         11 . The superchip of  claim 8 , wherein the CPU is further configured to:
 perform a security check to ensure that hardware signatures are acceptable for the first boot code and the second boot code.   
     
     
         12 . The superchip of  claim 8 , wherein initializing the first chiplet comprises configuring internal components of the first chiplet. 
     
     
         13 . The superchip of  claim 8 , wherein the compute die comprises an interconnection module, and, in initializing the second chiplet, the CPU is further configured to:
 send the first configuration instructions to the second chiplet via the interconnection module of the compute die.   
     
     
         14 . The superchip of  claim 1 , further comprising a third chiplet, wherein the CPU is further configured to:
 load a third boot code of the third chiplet; and   initialize the third chiplet based on the third boot code via second configuration instructions sent through the compute die,   wherein the initializing of the second chiplet and the third chiplet are performed in parallel.   
     
     
         15 . A first chiplet of a superchip comprising:
 a processor; and   a non-transitory computer readable storage medium storing instructions that, when executed, cause the processor to:
 load a first boot code of the first chiplet and a second boot code of a second chiplet of the superchip; 
 initialize the first chiplet based on the first boot code; and 
 initialize the second chiplet based on the second boot code via first configuration instructions sent through a compute die of the superchip. 
   
     
     
         16 . The first chiplet of  claim 15 , wherein the instructions further cause the processor to:
 configure the first chiplet as a main chiplet of the superchip through embedded fuse programming or hardwiring.   
     
     
         17 . The first chiplet of  claim 15 , wherein the first boot code and the second boot code are loaded from an external device via a boot loader module of the first chiplet. 
     
     
         18 . The first chiplet of  claim 15 , wherein the instructions further cause the processor to:
 perform a security check to ensure that hardware signatures are acceptable for the first boot code and the second boot code.   
     
     
         19 . The first chiplet of  claim 15 , wherein, in initializing the second chiplet, the instructions further cause the processor to:
 send the first configuration instructions to the second chiplet via an interconnection module of the compute die.   
     
     
         20 . The first chiplet of  claim 15 , wherein the instructions further cause the processor to:
 load a third boot code of a third chiplet of the superchip; and   initialize the third chiplet based on the third boot code via second configuration instructions sent through the compute die,   wherein the initializing of the second chiplet and the third chiplet are performed in parallel.