Systems and methods for controlling a vehicle system startup

Abstract

A method includes storing, by a microcontroller, cache data of the microcontroller into a dynamic random-access memory (DRAM) in response to the microcontroller receiving a power-off command. The method includes operating, by a DRAM controller, the DRAM in a standby state in response to the microcontroller storing the cache data into the DRAM. The method includes determining, by the DRAM controller and when the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof. The method includes determining, by the DRAM controller, whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof. The method includes storing, by the DRAM controller, the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied.

What is claimed is: 
     
         1 . A method for managing cache data stored by a vehicle control system, the method comprising:
 storing, by a microcontroller, the cache data of the microcontroller into a dynamic random-access memory (DRAM) in response to the microcontroller receiving a power-off command;   operating, by a DRAM controller, the DRAM in a standby state in response to the microcontroller storing the cache data into the DRAM, wherein the DRAM is operable in the standby state, an on state, and an off state;   determining, by the DRAM controller and when the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof;   determining, by the DRAM controller, whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof; and   storing, by the DRAM controller, the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied.   
     
     
         2 . The method of  claim 1  further comprising:
 determining, by the microcontroller, whether a power-on command is received; and 
 obtaining, by the microcontroller, the cache data from the ROM in response to the suspend to storage condition being satisfied. 
 
     
     
         3 . The method of  claim 2  further comprising obtaining, by the microcontroller, the cache data from the DRAM in response to the suspend to storage condition not being satisfied. 
     
     
         4 . The method of  claim 3  further comprising performing, by the microcontroller, one or more infotainment control routines in response to obtaining the cache data from one of the DRAM and the ROM. 
     
     
         5 . The method of  claim 1 , wherein:
 the time characteristic indicates an amount of time the DRAM operates in the standby state; and   the suspend to storage condition is satisfied in response to the amount of time being greater than a threshold amount of time.   
     
     
         6 . The method of  claim 1 , wherein:
 the charging characteristic indicates an amount of electrical charge of the DRAM; and   the suspend to storage condition is satisfied in response to the amount of electrical charge being less than a threshold amount of electrical charge.   
     
     
         7 . The method of  claim 1 , wherein the ROM has a sequential read speed of at least 4.2 gigabytes per second. 
     
     
         8 . The method of  claim 1 , wherein the ROM has a sequential write speed of at least 2.8 gigabytes per second. 
     
     
         9 . The method of  claim 1  further comprising performing a bootloader routine in response to the microcontroller receiving a power-on command and the DRAM operating in the off state. 
     
     
         10 . The method of  claim 1  further comprising performing a suspend to DRAM routine in response to the microcontroller receiving a power-on command and the DRAM operating in the standby state. 
     
     
         11 . A vehicle control system comprising:
 a dynamic random-access memory (DRAM), wherein the DRAM is operable in a standby state, an on state, and an off state;   a DRAM controller;   a microcontroller; and   a read-only memory (ROM), wherein:
 the DRAM, the DRAM controller, the microcontroller, and the ROM are communicably coupled to each other; 
 the microcontroller is configured to store cache data of the microcontroller into the DRAM in response to the microcontroller receiving a power-off command; 
 the DRAM controller is configured to operate the DRAM in one of the off state and the standby state in response to the microcontroller receiving the power-off command; 
 the DRAM controller is configured to determine, when the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof; 
 the DRAM controller is configured to determine whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof; and 
 the DRAM controller is configured to store the cache data of the DRAM into the ROM in response to the suspend to storage condition being satisfied. 
   
     
     
         12 . The system of  claim 11 , wherein the microcontroller is further configured to:
 determine whether a power-on command is received; and   obtain the cache data from the ROM in response to the suspend to storage condition being satisfied.   
     
     
         13 . The system of  claim 12 , wherein the microcontroller is further configured to obtain the cache data from the DRAM in response to the suspend to storage condition not being satisfied. 
     
     
         14 . The system of  claim 13 , wherein the microcontroller is further configured to perform one or more infotainment control routines in response to obtaining the cache data from one of the DRAM and the ROM. 
     
     
         15 . The system of  claim 11 , wherein:
 the time characteristic indicates an amount of time the DRAM operates in the standby state; and   the suspend to storage condition is satisfied in response to the amount of time being greater than a threshold amount of time.   
     
     
         16 . The system of  claim 11 , wherein:
 the charging characteristic indicates an amount of electrical charge of the DRAM; and   the suspend to storage condition is satisfied in response to the amount of electrical charge being less than a threshold amount of electrical charge.   
     
     
         17 . The system of  claim 11 , wherein the ROM has a sequential read speed of at least 4.2 gigabytes per second. 
     
     
         18 . The system of  claim 11 , wherein the ROM has a sequential write speed of at least 2.8 gigabytes per second. 
     
     
         19 . The system of  claim 11 , wherein the microcontroller is further configured to perform a bootloader routine in response to the microcontroller receiving a power-on command and the DRAM operating in the off state. 
     
     
         20 . The system of  claim 11 , wherein the microcontroller is further configured to perform a suspend to DRAM routine in response to the microcontroller receiving a power-on command and the DRAM operating in the standby state.