Inspection system

Abstract

An inspection system includes a semiconductor substrate on which a first inspection circuit and a second inspection circuit are formed, a measurer configured to measure a predetermined characteristic in each of the first inspection circuit and the second inspection circuit, and an estimator configured to estimate process variation when the first inspection circuit and the second inspection circuit are formed on the semiconductor substrate, based on a first measurement result obtained by the measurer measuring the first inspection circuit and a second measurement result obtained by the measurer measuring the second inspection circuit. A magnitude of a variation of the characteristic with respect to the process variation in the second inspection circuit differs from a magnitude of a variation of the characteristic with respect to the process variation in the first inspection circuit.

What is claimed is: 
     
         1 . An inspection system, comprising:
 a semiconductor substrate on which a first inspection circuit and a second inspection circuit are formed;   a measurer configured to measure a predetermined characteristic in each of the first inspection circuit and the second inspection circuit; and   an estimator configured to estimate process variation when the first inspection circuit and the second inspection circuit are formed on the semiconductor substrate, based on a first measurement result obtained by the measurer measuring the first inspection circuit and a second measurement result obtained by the measurer measuring the second inspection circuit, wherein   a magnitude of a variation of the characteristic with respect to the process variation in the second inspection circuit differs from a magnitude of a variation of the characteristic with respect to the process variation in the first inspection circuit.   
     
     
         2 . The inspection system according to  claim 1 , wherein
 the first inspection circuit is a ring oscillation circuit in which a plurality of first element circuits are connected in series and an output of a final stage is input to a foremost stage,   the second inspection circuit is a ring oscillation circuit in which a plurality of second element circuits are connected in series and an output of a final stage is input to a foremost stage, and   the characteristic is a frequency.   
     
     
         3 . The inspection system according to  claim 2 , wherein
 the first element circuit is a NOT circuit, and   the second element circuit is a NAND circuit.   
     
     
         4 . The inspection system according to  claim 3 , wherein
 the first element circuit includes a first PMOS transistor having a p-channel and a first NMOS transistor having an n-channel,   either one of a source or a drain of the first PMOS transistor is connected to a power supply potential,   the other of the source or the drain of the first PMOS transistor is connected to either one of a source or a drain of the first NMOS transistor and is connected to an output of the first element circuit,   the other of the source or the drain of the first NMOS transistor is connected to a common potential,   a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to an input of the first element circuit,   the second element circuit includes a second PMOS transistor and a third PMOS transistor each having a p-channel, and a second NMOS transistor and a third NMOS transistor each having an n-channel,   either one of a source or a drain of each of the second PMOS transistor and the third PMOS transistor is connected to the power supply potential,   the other of the source or the drain of each of the second PMOS transistor and the third PMOS transistor is connected to either one of a source or a drain of the second NMOS transistor and is connected to an output of the second element circuit,   the other of the source or the drain of the second NMOS transistor is connected to either one of a source or a drain of the third NMOS transistor,   the other of the source or the drain of the third NMOS transistor is connected to a common potential,   a gate of the second PMOS transistor and a gate of the third NMOS transistor are connected to an input of the second element circuit, and   a gate of the third PMOS transistor is connected to a gate of the second NMOS transistor and is connected to the power supply potential.   
     
     
         5 . The inspection system according to  claim 2 , wherein
 the first element circuit is a NOT circuit, and   the second element circuit is a NOR circuit.   
     
     
         6 . The inspection system according to  claim 5 , wherein
 the first element circuit includes a first PMOS transistor having a p-channel and a first NMOS transistor having an n-channel,   either one of a source or a drain of the first PMOS transistor is connected to a power supply potential,   the other of the source or the drain of the first PMOS transistor is connected to either one of a source or a drain of the first NMOS transistor and is connected to an output of the first element circuit,   the other of the source or the drain of the first NMOS transistor is connected to a common potential,   a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to an input of the first element circuit,   the second element circuit includes a fourth PMOS transistor and a fifth PMOS transistor each having a p-channel, and a fourth NMOS transistor and a fifth NMOS transistor each having an n-channel,   either one of a source or a drain of the fourth PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the fourth PMOS transistor is connected to either one of a source or a drain of the fifth PMOS transistor,   the other of the source or the drain of the fifth PMOS transistor is connected to either one of a source or a drain of each of the fourth NMOS transistor and the fifth NMOS transistor and is connected to an output of the second element circuit,   either one of a source or a drain of each of the fourth NMOS transistor and the fifth NMOS transistor is connected to the common potential,   a gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor are connected to an input of the second element circuit, and   a gate of the fifth PMOS transistor is connected to a gate of the fifth NMOS transistor and is connected to the common potential.   
     
     
         7 . The inspection system according to  claim 2 , wherein
 the first element circuit is a NAND circuit, and   the second element circuit is a NOR circuit.   
     
     
         8 . The inspection system according to  claim 7 , wherein
 the first element circuit includes a second PMOS transistor and a third PMOS transistor each having a p-channel, and a second NMOS transistor and a third NMOS transistor each having an n-channel,   either one of a source or a drain of each of the second PMOS transistor and the third PMOS transistor is connected to a power supply potential,   the other of the source or the drain of each of the second PMOS transistor and the third PMOS transistor is connected to either one of a source or a drain of the second NMOS transistor and is connected to an output of the second element circuit,   the other of the source or the drain of the second NMOS transistor is connected to either one of a source or a drain of the third NMOS transistor,   the other of the source or the drain of the third NMOS transistor is connected to a common potential,   a gate of the second PMOS transistor and a gate of the third NMOS transistor are connected to an input of the second element circuit,   a gate of the third PMOS transistor is connected to a gate of the second NMOS transistor and is connected to the power supply potential,   the second element circuit includes a fourth PMOS transistor and a fifth PMOS transistor each having a p-channel, and a fourth NMOS transistor and a fifth NMOS transistor each having an n-channel,   either one of a source or a drain of the fourth PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the fourth PMOS transistor is connected to either one of a source or a drain of the fifth PMOS transistor,   the other of the source or the drain of the fifth PMOS transistor is connected to either one of a source or a drain of each of the fourth NMOS transistor and the fifth NMOS transistor and is connected to the output of the second element circuit,   either one of a source or a drain of each of the fourth NMOS transistor and the fifth NMOS transistor is connected to the power supply potential,   a gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor are connected to the input of the second element circuit, and   a gate of the fifth PMOS transistor is connected to a gate of the fifth NMOS transistor and is connected to the common potential.   
     
     
         9 . The inspection system according to  claim 2 , wherein
 the first element circuit includes a plurality of NOT circuits, and respective inputs of the plurality of NOT circuits are connected to an input of the first element circuit, and   the second element circuit is a NOT circuit.   
     
     
         10 . The inspection system according to  claim 9 , wherein
 the first element circuit includes
 a NOT circuit having a sixth PMOS transistor having a p-channel and a sixth NMOS transistor having an n-channel; 
 a first dummy NOT circuit having a seventh PMOS transistor having a p-channel and a seventh NMOS transistor having an n-channel; and 
 a second dummy NOT circuit having an eighth PMOS transistor having a p-channel and an eighth NMOS transistor having an n-channel, 
   either one of a source or a drain of the sixth PMOS transistor is connected to a power supply potential,   the other of the source or the drain of the sixth PMOS transistor is connected to either one of a source or a drain of the sixth NMOS transistor and is connected to an output of the first element circuit,   the other of the source or the drain of the sixth NMOS transistor is connected to a common potential,   a gate of the sixth PMOS transistor and a gate of the sixth NMOS transistor are connected to an input of the first element circuit,   either one of a source or a drain of the seventh PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the seventh PMOS transistor is connected to either one of a source or a drain of the seventh NMOS transistor,   the other of the source or the drain of the seventh NMOS transistor is connected to the common potential,   a gate of the seventh PMOS transistor and a gate of the seventh NMOS transistor are connected to the input of the first element circuit,   either one of a source or a drain of the eighth PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the eighth PMOS transistor is connected to either one of a source or a drain of the eighth NMOS transistor,   the other of the source or the drain of the eighth NMOS transistor is connected to the common potential,   a gate of the eighth PMOS transistor and a gate of the eighth NMOS transistor are connected to the input of the first element circuit,   the second element circuit includes
 a ninth PMOS transistor having a p-channel; 
 a ninth NMOS transistor having an n-channel; 
 a first dummy interconnect; and 
 a second dummy interconnect, 
   either one of a source or a drain of the ninth PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the ninth transistor is connected to either one of a source or a drain of the ninth NMOS transistor and is connected to an output of the second element circuit,   the other of the source or the drain of the ninth NMOS transistor is connected to the common potential,   a gate of the ninth PMOS transistor and a gate of the ninth NMOS transistor are connected to an input of the second element circuit,   the first dummy interconnect is an interconnect having a same configuration as an interconnect from the input to the first dummy NOT circuit in the first element circuit, and   the second dummy interconnect is a interconnect having a same configuration as an interconnect from the input to the second dummy NOT circuit in the first element circuit.   
     
     
         11 . The inspection system according to  claim 2 , wherein
 the second element circuit has a same circuit configuration as the first element circuit, and   a gate width of a transistor constituting the second element circuit differs from a gate width of a transistor constituting the first element circuit corresponding to the transistor.   
     
     
         12 . The inspection system according to  claim 11 , wherein
 the first element circuit and the second element circuit are any one of a NOT circuit, a NAND circuit, or a NOR circuit.   
     
     
         13 . The inspection system according to  claim 11 , wherein
 the first element circuit is a NOT circuit having a tenth PMOS transistor having a p-channel and a tenth NMOS transistor having an n-channel,   either one of a source or a drain of the tenth PMOS transistor is connected to a power supply potential,   the other of the source or the drain of the tenth PMOS transistor is connected to either one of a source or a drain of the tenth NMOS transistor and is connected to an output of the first element circuit,   the other of the source or the drain of the tenth NMOS transistor is connected to a common potential,   a gate of the tenth PMOS transistor and a gate of the tenth NMOS transistor are connected to an input of the first element circuit,   the second element circuit is a NOT circuit having an eleventh PMOS transistor having a p-channel and an eleventh NMOS transistor having an n-channel,   either one of a source or a drain of the eleventh PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the eleventh PMOS transistor is connected to either one of a source or a drain of the eleventh NMOS transistor and is connected to an output of the second element circuit,   the other of the source or the drain of the eleventh NMOS transistor is connected to the common potential,   a gate of the eleventh PMOS transistor and a gate of the eleventh NMOS transistor are connected to an input of the second element circuit, and   a gate width of the eleventh PMOS transistor differs from a gate width of the tenth PMOS transistor, or a gate width of the eleventh NMOS transistor differs from a gate width of the tenth NMOS transistor.   
     
     
         14 . The inspection system according to  claim 1 , wherein
 the semiconductor substrate further includes a third inspection circuit,   the measurer measures the characteristic in the third inspection circuit,   the estimator estimates the process variation when the first inspection circuit, the second inspection circuit, and the third inspection circuit are formed on the semiconductor substrate, based on the first measurement result, the second measurement result, and a third measurement result obtained by the measurer measuring the third inspection circuit, and   a magnitude of a variation of the characteristic with respect to the process variation in the third inspection circuit differs from a magnitude of a variation of the characteristic with respect to the process variation in each of the first inspection circuit and the second inspection circuit.   
     
     
         15 . The inspection system according to  claim 14 , wherein
 the first inspection circuit is a ring oscillation circuit in which a plurality of first element circuits are connected in series and an output of a final stage is input to a foremost stage,   the second inspection circuit is a ring oscillation circuit in which a plurality of second element circuits are connected in series and an output of a final stage is input to a foremost stage,   the third inspection circuit is a ring oscillation circuit in which a plurality of third element circuits are connected in series and an output of a final stage is input to a foremost stage, and   the characteristic is a frequency.   
     
     
         16 . The inspection system according to  claim 15 , wherein
 the first element circuit is a NOT circuit,   the second element circuit is a NAND circuit, and   the third element circuit is a NOR circuit.   
     
     
         17 . The inspection system according to  claim 16 , wherein
 the first element circuit includes
 a first PMOS transistor having a p-channel; and 
 a first NMOS transistor having an n-channel, 
   either one of a source or a drain of the first PMOS transistor is connected to a power supply potential,   the other of the source or the drain of the first PMOS transistor is connected to either one of a source or a drain of the first NMOS transistor and is connected to an output of the first element circuit,   the other of the source or the drain of the first NMOS transistor is connected to a common potential,   a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to an input of the first element circuit,   the second element circuit includes
 a second PMOS transistor and a third PMOS transistor each having a p-channel; and 
 a second NMOS transistor and a third NMOS transistor each having an n-channel, 
   either one of a source or a drain of each of the second PMOS transistor and the third PMOS transistor is connected to the power supply potential,   the other of the source or the drain of each of the second PMOS transistor and the third PMOS transistor is connected to either one of a source or a drain of the second NMOS transistor and is connected to an output of the second element circuit,   the other of the source or the drain of the second NMOS transistor is connected to either one of a source or a drain of the third NMOS transistor,   the other of the source or the drain of the third NMOS transistor is connected to the common potential,   a gate of the second PMOS transistor and a gate of the third NMOS transistor are connected to an input of the second element circuit,   a gate of the third PMOS transistor is connected to a gate of the second NMOS transistor and is connected to the power supply potential,   the third element circuit includes
 a fourth PMOS transistor and a fifth PMOS transistor each having a p-channel; and 
 a fourth NMOS transistor and a fifth NMOS transistor each having an n-channel, 
   either one of a source or a drain of the fourth PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the fourth NMOS transistor is connected to either one of a source or a drain of the fifth NMOS transistor,   the other of the source or the drain of the fifth PMOS transistor is connected to either one of the source or the drain of each of the fourth NMOS transistor and the fifth NMOS transistor and is connected to an output of the third element circuit,   the other of the source or the drain of each of the fourth NMOS transistor and the fifth NMOS transistor is connected to the common potential,   a gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor are connected to an input of the third element circuit, and   a gate of the fifth PMOS transistor is connected to a gate of the fifth NMOS transistor and is connected to the common potential.   
     
     
         18 . The inspection system according to  claim 15 , wherein
 the first element circuit is a NOT circuit,   the second element circuit includes a plurality of NOT circuits, and respective inputs of the plurality of NOT circuits are connected to an input of the second element circuit, and   the third element circuit is a NOT circuit including a dummy interconnect.   
     
     
         19 . The inspection system according to  claim 18 , wherein
 the first element circuit includes
 a first PMOS transistor having a p-channel; and 
 a first NMOS transistor having an n-channel, 
   either one of a source or a drain of the first PMOS transistor is connected to a power supply potential,   the other of the source or the drain of the first PMOS transistor is connected to either one of a source or a drain of the first NMOS transistor and is connected to an output of the first element circuit,   the other of the source or the drain of the first NMOS transistor is connected to a common potential,   a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to an input of the first element circuit,   the second element circuit includes
 a NOT circuit having a sixth PMOS transistor having a p-channel and a sixth NMOS transistor having an n-channel; 
 a first dummy NOT circuit having a seventh PMOS transistor having a p-channel and a seventh NMOS transistor having an n-channel; and 
 a second dummy NOT circuit having an eighth PMOS transistor having a p-channel and an eighth NMOS transistor having an n-channel, 
   either one of a source or a drain of the sixth PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the sixth PMOS transistor is connected to either one of a source or a drain of the sixth NMOS transistor and is connected to an output of the second element circuit,   the other of the source or the drain of the sixth NMOS transistor is connected to the common potential,   a gate of the sixth PMOS transistor and a gate of the sixth NMOS transistor are connected to an input of the second element circuit,   either one of a source or a drain of the seventh PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the seventh PMOS transistor is connected to either one of a source or a drain of the seventh NMOS transistor,   the other of the source or the drain of the seventh NMOS transistor is connected to the common potential,   a gate of the seventh PMOS transistor and a gate of the seventh NMOS transistor are connected to an input of the second element circuit,   either one of a source or a drain of the eighth PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the eighth PMOS transistor is connected to either one of a source or a drain of the eighth NMOS transistor,   the other of the source or the drain of the eighth NMOS transistor is connected to the common potential,   a gate of the eighth PMOS transistor and a gate of the eighth NMOS transistor are connected to an input of the second element circuit,   the third element circuit includes
 a ninth PMOS transistor having a p-channel; 
 a ninth NMOS transistor having an n-channel; 
 a first dummy interconnect; and 
 a second dummy interconnect, 
   either one of a source or a drain of the ninth PMOS transistor is connected to the power supply potential,   the other of the source or the drain of the ninth PMOS transistor is connected to either one of a source or a drain of the ninth NMOS transistor and is connected to an output of the third element circuit,   the other of the source or the drain of the ninth NMOS transistor is connected to the common potential,   a gate of the ninth PMOS transistor and a gate of the ninth NMOS transistor are connected to an input of the third element circuit,   the first dummy interconnect is a interconnect having a same configuration as an interconnect from the input to the first dummy NOT circuit in the second element circuit, and   the second dummy interconnect is a interconnect having a same configuration as an interconnect from the input to the second dummy NOT circuit in the second element circuit.   
     
     
         20 . The inspection system according to  claim 14 , wherein
 the semiconductor substrate has a plurality of chip forming regions and a cutting region for cutting the plurality of chip forming regions into each of the chip forming regions, and   each of the first inspection circuit, the second inspection circuit, and the third inspection circuit is formed in the cutting region.