Power/thermal via for three-dimensional (3d) chip stacking

Abstract

A three-dimensional (3D) stacked chip is described. The 3D stacked chip includes a first die having a front-side surface and a backside surface, opposite the front-side surface. The backside surface on a front-side surface of a first redistribution layer (RDL). The 3D stacked chip also includes a second die having a front-side surface on the front-side surface of the first die and a backside surface being distal from the first RDL. The 3D stacked chip further includes a via extending from the backside surface of the second die to a back-end-of-line (BEOL) layer of the second die.

What is claimed is: 
     
         1 . A three-dimensional (3D) stacked chip, comprising:
 a first die having a front-side surface and a backside surface, opposite the front-side surface, the backside surface on a front-side surface of a first redistribution layer (RDL);   a second die having a front-side surface on the front-side surface of the first die and a backside surface being distal from the first RDL; and   a via extending from the backside surface of the second die to a back-end-of-line (BEOL) layer of the second die.   
     
     
         2 . The 3D stacked chip of  claim 1 , further comprising a second RDL having a front-side surface on the backside surface of the second die, the second RDL being distal from the first RDL, in which the via is directly coupled to the second RDL. 
     
     
         3 . The 3D stacked chip of  claim 1 , in which the second die comprises a substrate having an active layer coupled to the BEOL layer of the second die and distal from the backside surface of the second die, in which the via extends through the substrate and the active layer to the BEOL layer of the second die. 
     
     
         4 . The 3D stacked chip of  claim 3 , further comprising a thermal plate on the backside surface of the second die, in which the via is a thermal via that extends from the thermal plate and through the substrate and the active layer to the BEOL layer of the second die. 
     
     
         5 . The 3D stacked chip of  claim 4 , further comprising a thermal lead coupled to the thermal plate. 
     
     
         6 . The 3D stacked chip of  claim 3 , further comprising a second RDL on the backside surface of the second die, in which the via is a power via that extends from the second RDL through the substrate and the active layer to the BEOL layer of the second die. 
     
     
         7 . The 3D stacked chip of  claim 1 , in which the backside surface of the second die comprises a thermal interface layer. 
     
     
         8 . The 3D stacked chip of  claim 1 , further comprising a printed circuit board coupled to the first die through package bumps. 
     
     
         9 . The 3D stacked chip of  claim 1 , in which the front-side surface of the first die is directly bonded to the front-side surface of the second die to couple the BEOL layer of the second die to a BEOL layer of the first die. 
     
     
         10 . The 3D stacked chip of  claim 1 , further comprising a package substrate coupled to a backside surface of a second RDL on the backside surface of the second die. 
     
     
         11 . A method for fabricating a three-dimensional (3D) stacked chip, the method comprising:
 bonding a front-side surface of a second die to a front-side surface of a first die; and   forming a via extending from a backside surface of the second die to a back-end-of-line (BEOL) layer of the second die.   
     
     
         12 . The method of  claim 11 , further comprising:
 fabricating the first die having the front-side surface and a backside surface, opposite the front-side surface, the backside surface on a front-side surface of a first redistribution layer (RDL); and   fabricating the second die having the front-side surface on the front-side surface of the first die and the backside surface being distal from the first RDL.   
     
     
         13 . The method of  claim 12 , further comprising forming a second RDL having a front-side surface on the backside surface of the second die, the second RDL being distal from the first RDL, in which the via is directly coupled to the second RDL. 
     
     
         14 . The method of  claim 11 , in which the second die comprises a substrate having an active layer coupled to the BEOL layer of the second die and distal from the backside surface of the second die, in which the via extends through the substrate and the active layer to the BEOL layer of the second die. 
     
     
         15 . The method of  claim 14 , further comprising:
 forming a thermal plate on the backside surface of the second die, in which the via is a thermal via that extends from the thermal plate and through the substrate and the active layer to the BEOL layer of the second die; and   forming a thermal lead coupled to the thermal plate.   
     
     
         16 . The method of  claim 14 , further comprising forming a second RDL on the backside surface of the second die, in which the via is a power via that extends from the second RDL through the substrate and the active layer to the BEOL layer of the second die. 
     
     
         17 . The method of  claim 11 , in which the backside surface of the second die comprises a thermal interface layer. 
     
     
         18 . The method of  claim 11 , further comprising a printed circuit board coupled to the first die through package bumps. 
     
     
         19 . The method of  claim 11 , in which the front-side surface of the first die is directly bonded to the front-side surface of the second die to couple the BEOL layer of the second die to a BEOL layer of the first die. 
     
     
         20 . The method of  claim 11 , further comprising a package substrate coupled to a backside surface of a second RDL on the backside surface of the second die.