Multiple-Row Refresh for Usage-Based Disturbance Mitigation

Abstract

Apparatuses and techniques for implementing multiple-row refresh for usage-based disturbance mitigation are described. Multiple-row refresh for usage-based disturbance mitigation involves refreshing at least one victim row for usage-based disturbance mitigation during a refresh operation that involves another row. The victim row and the other row are effectively refreshed in parallel. Possible victim rows that can be refreshed can be coupled to components that are not shared by the other row associated with the refresh operation. Any count update procedures associated with refreshing the victim row and the other row can be performed at different times to avoid potential conflict on global input/output lines. Refreshing a victim row during a refresh operation of another row allows for refreshing extra victim rows.

What is claimed is: 
     
         1 . An apparatus comprising:
 a memory device comprising:
 at least one bank comprising multiple rows of memory cells; and 
 circuitry coupled to the at least one bank, the circuitry configured to:
 refresh a first row of multiple rows in a bank of the at least one bank while refreshing a second row of the multiple rows in the same bank as the first row, where the first row is a usage-based disturbance victim row, and the first row is coupled to a first read-write circuit that is different from a second read-write circuit coupled to the second row. 
 
   
     
     
         2 . The apparatus of  claim 1 , wherein
 the first row is in a first section of the bank, where the first section comprises rows of memory cells that are coupled to the first read-write circuit, and   the second row is in a second section of the bank, where the second section comprises rows of memory cells that are coupled to the second read-write circuit.   
     
     
         3 . The apparatus of  claim 2 , wherein the first section is not immediately adjacent to the second section. 
     
     
         4 . The apparatus of  claim 2 , wherein the first read-write circuit comprises:
 a set of digit lines coupled to a set of memory cells in the first section of the bank; and   a set of sense amplifiers coupled to the set of digit lines and configured to read data on the digit lines from the set of memory cells within the first section.   
     
     
         5 . The apparatus of  claim 2 , further comprising usage-based disturbance circuitry configured to identify at least one victim row of the multiple rows that is to be refreshed to mitigate usage-based disturbance within the bank,
 wherein the circuitry is configured to:
 determine that an identified victim row of the identified at least one victim row is coupled to a read-write circuit different from the second row based on determining that an address of the identified victim row is in a different, non-neighboring, section of the bank than the second row 
 refresh the first row as the identified victim row in response to determining the identified victim row is coupled to a read-write circuit different from the second row. 
   
     
     
         6 . The apparatus of  claim 1 , wherein the circuitry is configured to:
 determine the first row is coupled to a first read-write circuit that is different from the second read-write circuit coupled to the second row; and   refresh the first row while refreshing a second row in response to the determination that the first row is coupled to a first read-write circuit that is different from the second read-write circuit coupled to the second row.   
     
     
         7 . The apparatus of  claim 1 , wherein the circuitry is configured to:
 receive a command that allows for a quantity of refresh operations to be performed in series within the bank;   perform the quantity of refresh operations by at least refreshing the second row; and   perform at least one additional refresh operation by at least refreshing the first row, the performing of the at least one additional refresh occurring during a time interval in which the circuitry performs the quantity of refresh operations.   
     
     
         8 . The apparatus of  claim 1 , wherein the second row comprises a row that is being refreshed during a periodic refresh operation. 
     
     
         9 . The apparatus of  claim 1 , wherein
 the second row comprises a usage-based disturbance victim row, and   the circuitry is configured to refresh the first row while refreshing a second row in response to receiving a targeted refresh command to refresh the second row based on the second row being a usage-based disturbance victim row.   
     
     
         10 . The apparatus of  claim 1 , wherein
 each row of the multiple rows is configured to store data associated with usage-based disturbance within a subset of the memory cells, and   the circuitry is configured to update data associated with usage-based disturbance of the first row at a different time than updating data associated with usage-based disturbance of the second row.   
     
     
         11 . The apparatus of  claim 10 , wherein
 the data associated with usage-based disturbance comprises an activation count that represents a number of times a corresponding row has been accessed since a last refresh, and   the circuitry is configured to update the data associated with usage-based disturbance by performing an activation count update procedure.   
     
     
         12 . The apparatus of  claim 1 , wherein the circuitry is configured to:
 determine the first row is coupled to a same read-write circuit as the second row; and   abstain from refreshing the first row while refreshing the second row based on the first row being coupled to a same read-write circuit as the second row.   
     
     
         13 . The apparatus of  claim 1 , wherein the circuitry is configured to refresh a third row of multiple rows in the bank while refreshing the first and second rows, where the third row is a usage-based disturbance victim row, and the third row is coupled to a third read-write circuit that is different from the first and second read-write circuits. 
     
     
         14 . A method comprising:
 receiving, at a memory device, a command that allows for refreshing a first row of multiple rows of memory cells in a bank of the memory device; and   refreshing a second row in the same bank as the first row while refreshing the first row, where the second row is a usage-based disturbance victim row, and the second row is coupled to a second read-write circuit that is different from a first read-write circuit coupled to the first row.   
     
     
         15 . The method of  claim 14 , wherein
 the first row is in a first section of the bank, where the first section comprises rows of memory cells that are coupled to the first read-write circuit, and   the second row is in a second section of the bank, where the second section comprises rows of memory cells that are coupled to the second read-write circuit.   
     
     
         16 . The method of  claim 15 , wherein the first section is not immediately adjacent to the second section. 
     
     
         17 . The method of  claim 15 , further comprising:
 identifying at least one victim row of the multiple rows that is to be refreshed to mitigate usage-based disturbance within the bank; and   determining that an identified victim row of the identified at least one victim row is coupled to a read-write circuit different from the first row based on determining that an address of the identified victim row is in a different, non-neighboring, section of the bank than the second row,   wherein refreshing comprises refreshing the first row as the identified victim row in response to determining the identified victim row is coupled to a read-write circuit different from the first row.   
     
     
         18 . The method of  claim 14 , wherein
 each row of the multiple rows is configured to store data associated with usage-based disturbance within a subset of the memory cells, and   the method comprises updating data associated with usage-based disturbance of the first row at a different time than updating data associated with usage-based disturbance of the second row.   
     
     
         19 . An apparatus comprising:
 a memory device comprising:
 at least one bank comprising multiple rows of memory cells; and 
 circuitry coupled to the at least one bank, the circuitry configured to:
 receive a command that allows for a number of refresh operations to be performed in series within a bank of the at least one bank; 
 perform at least one refresh operation of the number of refresh operations by refreshing a first row of multiple rows in the bank, where the first row is coupled to a first read-write circuit; and 
 perform at least one additional refresh operation by at least refreshing a second row of multiple rows in the bank, where the second row is a usage-based disturbance victim row and is coupled to a second read-write circuit that is different from the first read-write circuit, 
 where the performing of the at least one additional refresh occurs during a time interval in which the circuitry performs the at least one refresh operation of the number of refresh operations. 
 
   
     
     
         20 . The apparatus of  claim 19 , wherein
 each row of the multiple rows is configured to store data associated with usage-based disturbance within a subset of the memory cells, and   the circuitry is configured to update data associated with usage-based disturbance of the first row at a different time than updating data associated with usage-based disturbance of the second row.