Fast path cpu mode for mixed xpu workloads

Abstract

One embodiment provides a processor device comprising a general-purpose processor including circuitry to provide an offload mode to execute an offloaded instruction and an accelerator device configured to execute a first portion of a data parallel workload, at least a second portion of the data parallel workload having a dependency on a scalar operation, and the scalar operation having a dependency on the first portion of the data parallel workload, cause the general-purpose processor to enter the offload mode after completion of at least the first portion of the data parallel workload, the general-purpose processor to enter the offload mode to perform the scalar operation, and execute the second portion of the data parallel workload based at least in part on output of the scalar operation.

What is claimed is: 
     
         1 . A processor device comprising:
 a general-purpose processor including circuitry to provide an offload mode to execute an offloaded instruction; and   an accelerator device configured to:
 execute a first portion of a data parallel workload, at least a second portion of the data parallel workload having a dependency on a scalar operation, and the scalar operation having a dependency on the first portion of the data parallel workload; 
 cause the general-purpose processor to enter the offload mode after completion of at least the first portion of the data parallel workload, the general-purpose processor to enter the offload mode to perform the scalar operation; and 
 execute the second portion of the data parallel workload based at least in part on output of the scalar operation. 
   
     
     
         2 . The processor device of  claim 1 , wherein to cause the general-purpose processor to enter the offload mode, the accelerator device is to trigger an interrupt on the general-purpose processor. 
     
     
         3 . The processor device of  claim 2 , wherein the interrupt is a non-maskable interrupt. 
     
     
         4 . The processor device of  claim 1 , wherein to enter the offload mode, the general-purpose processor is configured to:
 transition at least a portion of the general-purpose processor out of operating system control;   fetch a binary object from memory, the binary object to contain one or more instructions to perform the scalar operation;   execute the one or more instructions to perform the scalar operation;   write a result to the memory; and   transition the portion of the general-purpose processor into operating system control.   
     
     
         5 . The processor device of  claim 4 , wherein the one or more instructions include microcode executable by the general-purpose processor. 
     
     
         6 . The processor device of  claim 4 , wherein the offload mode is a non-privileged execution mode in which the one or more instructions have limited access to system resources. 
     
     
         7 . The processor device of  claim 1 , wherein to execute the second portion of the data parallel workload, the accelerator device is configured to select a data parallel routine from a plurality of data parallel routines, the accelerator device to select the data parallel routine based on the output of the scalar operation. 
     
     
         8 . The processor device of  claim 1 , wherein the second portion of the data parallel workload has a data dependency on the output of the scalar operation. 
     
     
         9 . The processor device of  claim 1 , wherein general-purpose processor is configured to enter the offload mode via a first processor core without impact to operations of a second processor core. 
     
     
         10 . The processor device of  claim 1 , wherein the accelerator device includes a graphics processor. 
     
     
         11 . A method comprising:
 specifying a workload for execution on an accelerator device that includes a scalar operation to be offloaded by the accelerator device to a general-purpose processor;   executing a first data parallel portion of the workload on the accelerator device to generate first output data;   causing the general-purpose processor to enter an offload mode in which instructions to perform the scalar operation are executable by the general-purpose processor independently of an operating system executed via the general-purpose processor;   executing instructions to perform the scalar operation on the general-purpose processor while in the offload mode to generate second output data, the second output data based at least in part on the first output data; and   executing a second data parallel portion of the workload on the accelerator device based at least in part on the second output data.   
     
     
         12 . The method of  claim 11 , comprising triggering execution of the workload on the accelerator device by the general-purpose processor on behalf of an application executed by the general-purpose processor. 
     
     
         13 . The method of  claim 11 , comprising causing the general-purpose processor to enter the offload mode via an interrupt to the general-purpose processor that is triggered by the accelerator device. 
     
     
         14 . The method of  claim 13 , comprising:
 receiving the interrupt at the general-purpose processor to enter the offload mode;   transitioning at least a portion of the general-purpose processor out of operating system control;   fetching a binary object from memory, the binary object containing one or more instructions to perform the scalar operation;   executing the one or more instructions to perform the scalar operation;   writing a result to the memory; and   transitioning the portion of the general-purpose processor into operating system control.   
     
     
         15 . The method of  claim 11 , wherein executing the second data parallel portion of the workload includes selecting, on the accelerator device, a data parallel routine from a plurality of data parallel routines based at least in part on the second output data and wherein the accelerator device includes a graphics processor. 
     
     
         16 . A heterogenous data processing system comprising:
 a base die including a plurality of chiplet sockets; and   a plurality of chiplets coupled with the plurality of chiplet sockets, the plurality of chiplets including:
 a first chiplet including an general-purpose processor including circuitry to provide an offload mode to execute an offloaded instruction; and 
 a second chiplet including an accelerator device configured to:
 execute a first portion of a data parallel workload, at least a second portion of the data parallel workload having a dependency on a scalar operation, and the scalar operation having a dependency on the first portion of the data parallel workload; 
 cause the general-purpose processor to enter the offload mode after completion of at least the first portion of the data parallel workload, the general-purpose processor to enter the offload mode to perform the scalar operation; and 
 execute the second portion of the data parallel workload based at least in part on output of the scalar operation. 
 
   
     
     
         17 . The heterogenous data processing system of  claim 16 , wherein to cause the general-purpose processor to enter the offload mode, the accelerator device is to trigger a non-maskable interrupt on the general-purpose processor. 
     
     
         18 . The heterogenous data processing system of  claim 17 , wherein to enter the offload mode, the general-purpose processor is configured to:
 transition at least a portion of the general-purpose processor out of operating system control;   fetch a binary object from memory, the binary object to contain one or more instructions to perform the scalar operation;   execute the one or more instructions to perform the scalar operation;   write a result to the memory; and   transition the portion of the general-purpose processor into operating system control.   
     
     
         19 . The heterogenous data processing system of  claim 18 , wherein to execute the second portion of the data parallel workload, the accelerator device is configured to select a data parallel routine from a plurality of data parallel routines, the accelerator device to select the data parallel routine based on the output of the scalar operation. 
     
     
         20 . The heterogenous data processing system of  claim 19 , wherein the accelerator device includes a graphics processor.