Methods and apparatus to structure waveguides for delays

Abstract

An example apparatus includes: a first metal layer including: a first delay line having a surface area; and a second metal layer including: a second delay line having a surface area overlapping the surface area of the first delay line; and an insulating layer coupled between the first metal layer and the second metal layer.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 a first metal layer including a first delay line having a surface area;   a second metal layer including a second delay line having a surface area overlapping the surface area of the first delay line; and   an insulating layer between the first metal layer and the second metal layer.   
     
     
         2 . The integrated circuit of  claim 1 , wherein:
 the first metal layer further includes a third delay line having a surface area; and   the second metal layer further includes a fourth delay line having a surface area overlapping the surface area of the third delay line.   
     
     
         3 . The integrated circuit of  claim 2 , wherein the first delay line further includes an endpoint, the second delay line further includes an endpoint, the third delay line further includes a terminal, the fourth delay line further includes an endpoint, and wherein the endpoint of the first delay line is coupled to the endpoint of the third delay line, and the endpoint of the second delay line is coupled to the endpoint of the fourth delay line. 
     
     
         4 . The integrated circuit of  claim 2 , further comprising:
 a first via is coupled to the first delay line and the third delay line through the insulating layer; and   a second via is coupled to the second delay line and the fourth delay line through the insulating layer.   
     
     
         5 . The integrated circuit of  claim 2 , wherein:
 the first delay line further includes a fin;   the second delay line further includes a fin overlapping the fin of the first delay line;   the third delay line further including a fin non-overlapping the fin of the first delay line and the fin of the second delay line; andthe fourth delay line further including a fin overlapping the fin of the third delay line.   
     
     
         6 . The integrated circuit of  claim 1 , wherein the insulating layer is a first insulating layer, the integrated circuit further comprising:
 a third metal layer further including a third delay line having a surface area; and   a fourth metal layer further including a fourth delay line having a surface area overlapping the surface area of the third delay line; and   a second insulating layer between the third metal layer and the fourth metal layer.   
     
     
         7 . The integrated circuit of  claim 6 , further comprising:
 a first via coupled to the first delay line and the third delay line through the first insulating layer and the second metal layer; and   a second via coupled to the second delay line and the fourth delay line through the third metal layer and the second insulating layer.   
     
     
         8 . An apparatus comprising:
 a first layer including a first waveguide having a surface, the first waveguide structured as first delay circuitry;   a second layer including a second waveguide having a surface overlapping the surface of the first waveguide, the second waveguide structured as second delay circuitry; and   a third layer between the first layer and the second layer.   
     
     
         9 . The apparatus of  claim 8 , further comprising:
 the first delay circuitry further having a third waveguide having a surface; and   the second delay circuitry further having a fourth waveguide having a surface overlapping the surface of the third waveguide.   
     
     
         10 . The apparatus of  claim 9 , wherein the first waveguide further has a terminal, the second waveguide further has a terminal, the third waveguide further has a terminal, the fourth waveguide further has a terminal, and wherein the terminal of the first waveguide is coupled to the terminal of the third waveguide, and the terminal of the second waveguide is coupled to the terminal of the fourth waveguide. 
     
     
         11 . The apparatus of  claim 9 , wherein the first layer further having the fourth waveguide, the second layer further having the third waveguide, and the apparatus further comprising:
 a first via is coupled to the first waveguide and the third waveguide; and   a second via is coupled to the second waveguide and the fourth waveguide.   
     
     
         12 . The apparatus of  claim 9 , further comprising:
 the first waveguide further having a fin;   the second waveguide further having a fin overlapping the fin of the first waveguide;   the third waveguide further having a fin non-overlapping the fin of the first waveguide and the fin of the second waveguide; and   the fourth waveguide further having a fin overlapping the fin of the third waveguide.   
     
     
         13 . The apparatus of  claim 9 , further comprising:
 the first delay circuitry further having a fifth waveguide having a surface; and   the second delay circuitry further having a sixth waveguide having a surface overlapping the surface of the fifth waveguide.   
     
     
         14 . The apparatus of  claim 13 , further comprising:
 the first delay circuitry further having:
 a first via coupled to the first waveguide and the third waveguide; and 
 a second via coupled to the third waveguide and the fifth waveguide; and 
   the second delay circuitry further having:
 a third via coupled to the second waveguide and the fourth waveguide; and 
 a fourth via coupled to the fourth waveguide and the sixth waveguide. 
   
     
     
         15 . An apparatus comprising:
 a first layer including a first electrical trace having a surface area; and   a second layer including a second electrical trace having a surface area overlapping the surface area of the first electrical trace;   a third layer coupled between the first layer and the second layer;   a first analog-to-digital converter (ADC) coupled to the first electrical trace and the second electrical trace; and   a second ADC coupled to the first ADC by the first electrical trace and the second electrical trace.   
     
     
         16 . The apparatus of  claim 15 , further comprising:
 the first layer further includes a third electrical trace having a surface area; and   the second layer further includes a fourth electrical trace having a surface area overlapping the surface area of the third electrical trace.   
     
     
         17 . The apparatus of  claim 16 , wherein the first electrical trace further has a terminal, the second electrical trace further has a terminal, the third electrical trace further has a terminal, the fourth electrical trace further has a terminal, the terminal of the first electrical trace coupled to the terminal of the third electrical trace, and the terminal of the second electrical trace coupled to the terminal of the fourth electrical trace. 
     
     
         18 . The apparatus of  claim 17 , wherein the first electrical trace and the third electrical trace are configured to form a first plate, the second electrical trace and the fourth electrical trace are configured to form a second plate, the first plate and the second plate to have overlapping surfaces. 
     
     
         19 . The apparatus of  claim 16 , further comprising:
 a first via configured to couple the first electrical trace to the third electrical trace through the third layer; and   a second via configured to couple the second electrical trace and the fourth electrical trace through the third layer.   
     
     
         20 . The apparatus of  claim 16 , further comprising:
 the first electrical trace further having a fin;   the second electrical trace further having a fin overlapping the fin of the first electrical trace;   the third electrical trace further having a fin non-overlapping the fin of the first electrical trace and the fin of the second electrical trace; and   the fourth electrical trace further having a fin overlapping the fin of the third electrical trace, the fins are configured to increase the surface area between electrical traces of the first layer and electrical traces of the second layer.