Receiver, data receiving structure, and memory

Abstract

A receiver includes: a first-stage sampling circuit, a second-stage sampling circuit, and an adjusting circuit. The first-stage sampling circuit is configured to generate and output a sampling signal and a complementary sampling signal based on an input signal and a reference signal in a sampling phase. The second-stage sampling circuit is configured to perform amplification on a voltage difference between the sampling signal and the complementary sampling signal in the sampling phase and output a data signal and a complementary data signal. The adjusting circuit is configured to adjust a signal amplification speed of the second-stage sampling circuit based on the sampling signal and the complementary sampling signal in the sampling phase.

What is claimed is: 
     
         1 . A receiver, comprising:
 a first-stage sampling circuit configured to receive an input signal and a reference signal, and generate and output a sampling signal and a complementary sampling signal based on the input signal and the reference signal in a sampling phase,   wherein if a potential of the input signal is greater than a potential of the reference signal, a potential of the generated complementary sampling signal is greater than a potential of the generated sampling signal; and if the potential of the reference signal is greater than the potential of the input signal, the potential of the generated sampling signal is greater than the potential of the generated complementary sampling signal;   a second-stage sampling circuit configured to receive the sampling signal and the complementary sampling signal, and perform amplification on a voltage difference between the sampling signal and the complementary sampling signal in the sampling phase and output a data signal and a complementary data signal,   wherein if the potential of the sampling signal is greater than the potential of the complementary sampling signal, the generated complementary data signal is at a high level and the generated data signal is at a low level; and if the potential of the complementary sampling signal is greater than the potential of the sampling signal, the generated data signal is at a high level and the generated complementary data signal is at a low level; and   an adjusting circuit connected to the first-stage sampling circuit and the second-stage sampling circuit, separately, and configured to receive the sampling signal and the complementary sampling signal, and adjust a signal amplification speed of the second-stage sampling circuit based on the sampling signal and the complementary sampling signal in the sampling phase.   
     
     
         2 . The receiver according to  claim 1 , wherein:
 the first-stage sampling circuit is further configured to discharge an output terminal thereof based on a clock signal or a complementary clock signal in a precharge phase, to generate and output the sampling signal and the complementary sampling signal at a low level;   the second-stage sampling circuit is further configured to precharge an output terminal thereof based on the clock signal or the complementary clock signal in the precharge phase, to generate and output the data signal and the complementary data signal at a high level; and   the adjusting circuit is further configured to adjust a precharge speed of the second-stage sampling circuit based on the sampling signal and the complementary sampling signal in the precharge phase.   
     
     
         3 . The receiver according to  claim 2 , wherein the receiver is in the sampling phase when the clock signal is at a high level or the complementary clock signal is at a low level; and the receiver is in the precharge phase when the clock signal is at a low level or the complementary clock signal is at a high level. 
     
     
         4 . The receiver according to  claim 1 , wherein the adjusting circuit comprises:
 a first pull-up transistor, with a first terminal configured to receive a first power supply voltage, a second terminal connected to a first output terminal of the second-stage sampling circuit, and a control terminal configured to receive the sampling signal; and   a second pull-up transistor, with a first terminal configured to receive the first power supply voltage, a second terminal connected to a second output terminal of the second-stage sampling circuit, and a control terminal configured to receive the complementary sampling signal,   wherein the first output terminal is configured to output the data signal, and the second output terminal is configured to output the complementary data signal.   
     
     
         5 . The receiver according to  claim 4 , wherein the adjusting circuit further comprises: a first equalization transistor, with a first terminal connected to the first output terminal, a second terminal connected to the second output terminal, and a control terminal configured to receive the clock signal. 
     
     
         6 . The receiver according to  claim 1 , wherein the adjusting circuit is driven based on the first power supply voltage, and the first-stage sampling circuit and the second-stage sampling circuit are driven based on a second power supply voltage, wherein a voltage value of the first power supply voltage is greater than that of the second power supply voltage. 
     
     
         7 . The receiver according to  claim 1 , wherein the adjusting circuit comprises:
 a plurality of first pull-up control circuits configured to adjust a pull-up speed of the first output terminal of the second-stage sampling circuit based on a first control signal and the sampling signal, wherein each of the plurality of first pull-up control circuits comprises a first control transistor and a first pull-up transistor connected in series, and the first control signal comprises a plurality of first control sub-signals in one-to-one correspondence to first control transistors, wherein a first terminal of each of the first control transistors is configured to receive the first power supply voltage, a second terminal of the first control transistor is connected to a first terminal of the first pull-up transistor, a second terminal of the first pull-up transistor is connected to the first output terminal of the second-stage sampling circuit, a control terminal of the first control transistor is configured to receive a corresponding one of the plurality of first control sub-signals, and a control terminal of the first pull-up transistor is configured to receive the sampling signal; and   a plurality of second pull-up control circuits configured to adjust a pull-up speed of the second output terminal of the second-stage sampling circuit based on a second control signal and the complementary sampling signal,   wherein each of the plurality of second pull-up control circuits comprises a second control transistor and a second pull-up transistor connected in series, and the second control signal comprises a plurality of second control sub-signals in one-to-one correspondence to second control transistors, wherein a first terminal of each of the second control transistors is configured to receive the first power supply voltage, a second terminal of the second control transistor is connected to a first terminal of the second pull-up transistor, a second terminal of the second pull-up transistor is connected to the second output terminal of the second-stage sampling circuit, a control terminal of the second control transistor is configured to receive a corresponding one of the plurality of second control sub-signals, and a control terminal of the second pull-up transistor is configured to receive the complementary sampling signal, and   wherein the first output terminal is configured to output the data signal, and the second output terminal is configured to output the complementary data signal.   
     
     
         8 . The receiver according to  claim 7 , further comprising: a regulation control circuit connected to the plurality of first pull-up control circuits and the plurality of second pull-up control circuits, separately, and configured to regulate the first control signal and the second control signal, and acquire and latch the current first control signal and second control signal based on an optimal eye diagram of the data signal and the complementary data signal. 
     
     
         9 . The receiver according to  claim 1 , wherein the first-stage sampling circuit comprises:
 a first driver transistor, with a control terminal configured to receive the complementary clock signal and a first terminal configured to receive the second power supply voltage;   a first P-type transistor, with a control terminal configured to receive the input signal, a first terminal connected to a second terminal of the first driver transistor, and a second terminal configured to output the sampling signal;   a second P-type transistor, with a control terminal configured to receive the reference signal, a first terminal connected to the second terminal of the first driver transistor, and a second terminal configured to output the complementary sampling signal;   a first N-type transistor, with a control terminal configured to receive the complementary clock signal, a first terminal connected to the second terminal of the first P-type transistor, and a second terminal grounded; and   a second N-type transistor, with a control terminal connected to the control terminal of the first N-type transistor, a first terminal connected to the second terminal of the second P-type transistor, and a second terminal grounded.   
     
     
         10 . The receiver according to  claim 1 , wherein the second-stage sampling circuit comprises:
 a second driver transistor, with a control terminal configured to receive the clock signal and a first terminal configured to receive the second power supply voltage;   a third driver transistor, with a control terminal configured to receive the clock signal and a first terminal configured to receive the second power supply voltage;   a third P-type transistor, with a control terminal connected to a second terminal of the second driver transistor and configured to output the complementary data signal, a first terminal configured to receive the second power supply voltage, and a second terminal connected to the second terminal of the second driver transistor;   a fourth P-type transistor, with a control terminal connected to a second terminal of the third driver transistor and configured to output the data signal, a first terminal configured to receive the second power supply voltage, and a second terminal connected to the second terminal of the third driver transistor;   a third N-type transistor, with a control terminal connected to the second terminal of the second driver transistor and a first terminal connected to the second terminal of the second driver transistor;   a fourth N-type transistor, with a control terminal connected to the second terminal of the third driver transistor and a first terminal connected to the second terminal of the third driver transistor;   a fifth N-type transistor, with a control terminal configured to receive the sampling signal, a first terminal connected to a second terminal of the third N-type transistor, and a second terminal grounded; and   a sixth N-type transistor, with a control terminal configured to receive the complementary sampling signal, a first terminal connected to a second terminal of the fourth N-type transistor, and a second terminal grounded.   
     
     
         11 . The receiver according to  claim 10 , wherein the second-stage sampling circuit further comprises: a second equalization transistor, with a first terminal connected to the first terminal of the third N-type transistor, a second terminal connected to the first terminal of the fourth N-type transistor, and a control terminal configured to receive the complementary clock signal. 
     
     
         12 . The receiver according to  claim 1 , further comprising: a decision feedback equalization circuit configured to feedback-adjust the potential of the sampling signal and the potential of the complementary sampling signal based on the data signal and the complementary data signal that have been previously output. 
     
     
         13 . A data receiving structure, comprising: N data receiving units, the N data receiving units being sequentially driven based on N phases of clocks, and each data receiving unit in the N data receiving units being set based on the receiver according to  claim 1 , N being a positive integer. 
     
     
         14 . A memory receiving input data based on the receiver according to  claim 1 . 
     
     
         15 . A memory receiving input data based on the data receiving structure according to  claim 13 .