Phase-Change Memory Device and Method

Abstract

A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

What is claimed is: 
     
         1 . A device comprising:
 a first dielectric layer over a word line;   a first phase-change random-access memory (PCRAM) cell in the first dielectric layer, wherein the first PCRAM cell comprises a phase-change material (PCM) layer sandwiched between a lower electrode and an upper electrode, wherein the lower electrode is electrically coupled to the word line, wherein a bottom surface of the PCM layer is above a bottom surface of the first dielectric layer and a top surface of the PCM layer is below a top surface of the first dielectric layer; and   a bit line over the first dielectric layer, wherein the upper electrode is electrically coupled to the bit line.   
     
     
         2 . The device of  claim 1 , wherein the PCM layer comprises GeSbTe (GST). 
     
     
         3 . The device of  claim 1  further comprising a second PCRAM cell in the first dielectric layer, wherein the second PCRAM cell is electrically coupled to the word line. 
     
     
         4 . The device of  claim 1 , wherein the upper electrode extends on a top surface of the first dielectric layer. 
     
     
         5 . The device of  claim 1 , wherein the lower electrode comprises a barrier layer. 
     
     
         6 . The device of  claim 1 , wherein a thickness of the PCM layer is greater than a thickness of the lower electrode. 
     
     
         7 . The device of  claim 1 , wherein a width of the PCM layer is greater than a width of the lower electrode. 
     
     
         8 . The device of  claim 1 , wherein a width of the upper electrode is greater than a width of the PCM layer. 
     
     
         9 . A memory array comprising:
 a plurality of transistors on a substrate;   a dielectric layer over the plurality of transistors; and   a plurality of phase-change random-access memory (PCRAM) cells over the dielectric layer, wherein each PCRAM cell is electrically coupled to a respective transistor, wherein each PCRAM cell extends through the dielectric layer, wherein each PCRAM cell comprises:   a top electrode on a top surface of the dielectric layer;   a phase-change material (PCM) under the top electrode, wherein a top surface of the PCM is closer to the transistor than a top surface of the dielectric layer; and   a bottom electrode under the PCM.   
     
     
         10 . The memory array of  claim 9 , wherein a bottom surface of the top electrode is closer to the transistor than a top surface of the dielectric layer. 
     
     
         11 . The memory array of  claim 9 , wherein a portion of the top electrode on the PCM has a greater thickness than a portion of the top electrode on the top surface of the dielectric layer. 
     
     
         12 . The memory array of  claim 9 , wherein the bottom electrode of each PCRAM cell is electrically coupled to a source/drain region of each respective transistor. 
     
     
         13 . The memory array of  claim 9 , wherein a thickness of the PCM is smaller than a thickness of the dielectric layer. 
     
     
         14 . The memory array of  claim 9  further comprising a plurality of word lines that electrically couple each PCRAM cell to each respective transistor. 
     
     
         15 . A device comprising:
 a conductive feature over a substrate;   an insulating layer over the conductive feature;   a barrier layer on the conductive feature and on a lower sidewall of the insulating layer;   a first conductive material on the barrier layer;   a phase-change material (PCM) on the barrier layer and on the first conductive material; and   a second conductive material on the PCM, on a top surface of the insulating layer, and on an upper sidewall of the insulating layer.   
     
     
         16 . The device of  claim 15 , wherein a top surface of the PCM is convex. 
     
     
         17 . The device of  claim 15 , wherein top surfaces of the barrier layer and the first conductive material are level. 
     
     
         18 . The device of  claim 15 , wherein the second conductive material is free of the barrier layer. 
     
     
         19 . The device of  claim 15 , wherein the first conductive material comprises titanium nitride. 
     
     
         20 . The device of  claim 15 , wherein the top surface of the insulating layer is free of the PCM.