Thin-film transistor array substrate and display device including same

Abstract

A thin-film transistor array substrate and a display device including the same are discussed. The thin-film transistor array substrate can include a buffer layer disposed over a base substrate and a thin-film transistor. Parasitic capacitance is minimized by minimizing the area where the gate electrode overlaps the conductorization region. The breakdown characteristics of the thin-film transistor are improved by minimizing the overlapping area and improving the thickness uniformity of the gate insulating layer. The resolution and performance of the display device are improved by reducing the size of the thin-film transistor disposed in the display device while improving the characteristics of the thin-film transistor. The process steps and the masks are reduced and the process optimization is achieved. Further, the resistance of the gate electrode is reduced, the switching speed of the thin-film transistor is improved, and the power loss is reduced, thereby contributing to low power consumption.

What is claimed is: 
     
         1 . A thin-film transistor array substrate comprising:
 a base substrate;   a buffer layer disposed over the base substrate, and comprising an open area exposing a portion of the base substrate and a first slope having an inverted tapered shape and exposed through the open area; and   a first thin-film transistor,   wherein the first thin-film transistor comprises:
 a first active pattern comprising a first channel region comprising a first portion disposed over the first slope of the buffer layer and a second portion disposed over a top surface of the base substrate under the first slope of the buffer layer, a first conductorization region disposed over a top surface of the buffer layer, and a second conductorization region disposed over the top surface of the base substrate; 
 a first gate insulating layer comprising a first slope portion disposed over the first portion of the first channel region and a first horizontal portion disposed over the second portion of the first channel region; and 
 a first gate electrode disposed over the first slope portion and the first horizontal portion of the first gate insulating layer and overlapping the first channel region. 
   
     
     
         2 . The thin-film transistor array substrate of  claim 1 , wherein a portion of the first conductorization region is self-aligned with the first slope portion of the first gate insulating layer, and
 wherein a portion of the second conductorization region is self-aligned with the first horizontal portion of the first gate insulating layer.   
     
     
         3 . The thin-film transistor array substrate of  claim 1 , wherein the second conductorization region does not overlap the first gate electrode. 
     
     
         4 . The thin-film transistor array substrate of  claim 1 , wherein the first conductorization region overlaps the first slope of the buffer layer, and the second conductorization region does not overlap the first slope of the buffer layer. 
     
     
         5 . The thin-film transistor array substrate of  claim 1 , wherein the first conductorization region and the second conductorization region are spaced apart from each other in a direction parallel to the top surface of the base substrate. 
     
     
         6 . The thin-film transistor array substrate of  claim 1 , wherein a top portion of the first slope portion of the first gate insulating layer is in contact with a side surface of the first conductorization region. 
     
     
         7 . The thin-film transistor array substrate of  claim 6 , wherein the first gate electrode comprises an inner surface in contact with the first slope portion and the first horizontal portion of the first gate insulating layer and an outer surface opposite the inner surface, and
 wherein the outer surface of the first gate electrode is aligned perpendicular to the top portion of the first slope portion of the first gate insulating layer.   
     
     
         8 . The thin-film transistor array substrate of  claim 6 , wherein the first gate electrode comprises an inner surface in contact with the first slope portion and the first horizontal portion of the first gate insulating layer and an outer surface opposite the inner surface, and
 wherein the outer surface of the first gate electrode protrudes beyond the top portion of the first slope portion of the first gate insulating layer.   
     
     
         9 . The thin-film transistor array substrate of  claim 6 , wherein the first gate electrode comprises an inner surface in contact with the first slope portion and the first horizontal portion of the first gate insulating layer and an outer surface opposite the inner surface, and
 wherein the outer surface of the first gate electrode has a tapered shape.   
     
     
         10 . The thin-film transistor array substrate of  claim 1 , wherein the first gate electrode comprises an inner surface in contact with the first slope portion and the first horizontal portion of the first gate insulating layer and an outer surface opposite the inner surface, and
 wherein the outer surface of the first gate electrode has curvatures corresponding to surface shapes of the first slope portion and the first horizontal portion of the first gate insulating layer.   
     
     
         11 . The thin-film transistor array substrate of  claim 1 , wherein a portion of the first slope portion of the first gate insulating layer is in direct contact with the first portion of the first channel region, and another portion of the first slope portion of the first gate insulating layer is in direct contact with the first slope of the buffer layer, and
 wherein a portion of the first horizontal portion of the first gate insulating layer is in direct contact with the second portion of the first channel region, and another portion of the first horizontal portion of the first gate insulating layer is in direct contact with the top surface of the base substrate.   
     
     
         12 . The thin-film transistor array substrate of  claim 11 , further comprising a gate connecting electrode connected to the first gate electrode,
 wherein the gate connecting electrode is disposed over the other portion of the first slope portion of the first gate insulating layer and the other portion of the first horizontal portion of the first gate insulating layer.   
     
     
         13 . The thin-film transistor array substrate of  claim 12 , wherein the gate connecting electrode is formed of a same material as the first gate electrode. 
     
     
         14 . The thin-film transistor array substrate of  claim 12 , wherein the gate connecting electrode covers the first gate insulating layer over the first slope of the buffer layer. 
     
     
         15 . The thin-film transistor array substrate of  claim 1 , wherein the buffer layer further comprises a second slope exposed through the open area, facing the first slope in a first direction, and having an inverted tapered shape,
 wherein the thin-film transistor array substrate further comprises a second thin-film transistor disposed over a region including the second slope of the buffer layer and sharing the second conductorization region with the first thin-film transistor.   
     
     
         16 . The thin-film transistor array substrate of  claim 15 , wherein the first active pattern further comprises a second channel region comprising a third portion disposed over the second slope of the buffer layer and a fourth portion disposed over the top surface of the base substrate under the second slope of the buffer layer and a third conductorization region disposed over the top surface of the buffer layer,
 wherein the first gate insulating layer further comprises a second slope portion disposed over the third portion of the second channel region and a second horizontal portion disposed over the fourth portion of the second channel region, and   wherein the second thin-film transistor comprises:
 the second channel region, the second conductorization region, and the third conductorization region of the first active pattern; 
 the second slope portion and the second horizontal portion of the first gate insulating layer; and 
 a second gate electrode disposed over the second slope portion and the second horizontal portion of the first gate insulating layer and overlapping the second channel region. 
   
     
     
         17 . The thin-film transistor array substrate of  claim 16 , wherein a portion of the first conductorization region is self-aligned with the first slope portion of the first gate insulating layer,
 wherein a portion of the second conductorization region is self-aligned with the first horizontal portion of the first gate insulating layer,   wherein another portion of the second conductorization region is self-aligned with the second horizontal portion of the first gate insulating layer, and   wherein a portion of the third conductorization region is self-aligned with the second slope portion of the first gate insulating layer.   
     
     
         18 . The thin-film transistor array substrate of  claim 16 , wherein the second conductorization region does not overlap the first or second gate electrode. 
     
     
         19 . The thin-film transistor array substrate of  claim 16 , wherein the first conductorization region overlaps the first slope of the buffer layer,
 wherein the third conductorization region overlaps the second slope of the buffer layer, and   wherein the second conductorization region does not overlap the first or second slope of the buffer layer.   
     
     
         20 . The thin-film transistor array substrate of  claim 16 , wherein the first conductorization region, the second conductorization region, and the third conductorization region are spaced apart from each other in a direction parallel to the top surface of the base substrate. 
     
     
         21 . The thin-film transistor array substrate of  claim 16 , wherein a portion of the first slope portion of the first gate insulating layer is in direct contact with the first portion of the first channel region, and another portion of the first slope portion of the first gate insulating layer is in direct contact with the first slope of the buffer layer,
 wherein a portion of the first horizontal portion of the first gate insulating layer is in direct contact with the second portion of the first channel region, and another portion of the first horizontal portion of the first gate insulating layer is in direct contact with the top surface of the base substrate,   wherein a portion of the second slope portion of the first gate insulating layer is in direct contact with the third portion of the second channel region, and another portion of the second slope portion of the first gate insulating layer is in direct contact with the second slope of the buffer layer, and   wherein a portion of the second horizontal portion of the first gate insulating layer is in direct contact with the fourth portion of the second channel region, and another portion of the second horizontal portion of the first gate insulating layer is in direct contact with the top surface of the base substrate.   
     
     
         22 . The thin-film transistor array substrate of  claim 21 , wherein the buffer layer further comprises third and fourth slopes exposed through the open area, facing each other in a second direction intersecting the first direction, and having an inverted tapered shape, and
 wherein the first gate insulating layer further comprises a third slope portion disposed over the third slope of the buffer layer, a third horizontal portion disposed over the base substrate under the third slope portion, a fourth slope portion disposed over the fourth slope of the buffer layer, and a fourth horizontal portion disposed over the base substrate under the fourth slope portion.   
     
     
         23 . The thin-film transistor array substrate of  claim 22 , further comprising a gate connecting electrode connected to the first gate electrode and the second gate electrode,
 wherein the gate connecting electrode is disposed over the other portion of the first slope portion of the first gate insulating layer, the other portion of the first horizontal portion of the first gate insulating layer, the other portion of the second slope portion of the first gate insulating layer, the other portion of the second horizontal portion of the first gate insulating layer, the third slope portion of the first gate insulating layer, the third horizontal portion of the first gate insulating layer, the fourth slope portion of the first gate insulating layer, and the fourth horizontal portion of the first gate insulating layer.   
     
     
         24 . The thin-film transistor array substrate of  claim 23 , wherein the gate connecting electrode is formed of a same material as the first and second gate electrodes. 
     
     
         25 . The thin-film transistor array substrate of  claim 23 , further comprising a gate connecting line disposed over the buffer layer and connected to the gate connecting electrode. 
     
     
         26 . The thin-film transistor array substrate of  claim 25 , wherein the first gate insulating layer further comprises an extension portion disposed between the buffer layer and the gate connecting line. 
     
     
         27 . The thin-film transistor array substrate of  claim 25 , wherein the gate connecting line does not overlap the first active pattern. 
     
     
         28 . A display device comprising:
 a substrate;   a circuit element layer disposed over the substrate; and   an emitting element disposed over the circuit element layer,   wherein the circuit element layer comprises:
 a buffer layer disposed over the substrate, and comprising an open area exposing a portion of the substrate and a first slope having an inverted tapered shape and exposed through the open area; and 
 a first thin-film transistor, 
   wherein the first thin-film transistor comprises:
 a first active pattern comprising a first channel region comprising a first portion disposed over the first slope of the buffer layer and a second portion disposed over a top surface of the substrate under the first slope of the buffer layer, a first conductorization region disposed over a top surface of the buffer layer, and a second conductorization region disposed over the top surface of the substrate; 
 a first gate insulating layer comprising a first slope portion disposed over the first portion of the first channel region and a first horizontal portion disposed over the second portion of the first channel region; and 
 a first gate electrode disposed over the first slope portion and the first horizontal portion of the first gate insulating layer and overlapping the first channel region. 
   
     
     
         29 . The display device of  claim 28 , wherein a portion of the first conductorization region is self-aligned with the first slope portion of the first gate insulating layer, and
 wherein a portion of the second conductorization region is self-aligned with the first horizontal portion of the first gate insulating layer.   
     
     
         30 . The display device of  claim 28 , wherein the second conductorization region does not overlap the first gate electrode. 
     
     
         31 . The display device of  claim 28 , wherein the first conductorization region overlaps the first slope of the buffer layer, and the second conductorization region does not overlap the first slope of the buffer layer. 
     
     
         32 . The display device of  claim 28 , wherein the buffer layer further comprises a second slope exposed through the open area, facing the first slope in a first direction, and having an inverted tapered shape, and
 wherein the circuit element layer further comprises a second thin-film transistor disposed over a region including the second slope of the buffer layer and sharing the second conductorization region with the first thin-film transistor.   
     
     
         33 . The display device of  claim 32 , wherein the first active pattern further comprises a second channel region comprising a third portion disposed over the second slope of the buffer layer and a fourth portion disposed over the top surface of the substrate under the second slope of the buffer layer and connected to the second conductorization region and a third conductorization region disposed over the top surface of the buffer layer,
 wherein the first gate insulating layer further comprises a second slope portion disposed over the third portion of the second channel region and a second horizontal portion disposed over the fourth portion of the second channel region, and   wherein the second thin-film transistor comprises:
 the second channel region, the second conductorization region, and the third conductorization region of the first active pattern; 
 the second slope portion and the second horizontal portion of the first gate insulating layer; and 
 a second gate electrode disposed over the second slope portion and the second horizontal portion of the first gate insulating layer and overlapping the second channel region. 
   
     
     
         34 . The display device of  claim 33 , wherein a portion of the first conductorization region is self-aligned with the first slope portion of the first gate insulating layer,
 wherein a portion of the second conductorization region is self-aligned with the first horizontal portion of the first gate insulating layer,   wherein another portion of the second conductorization region is self-aligned with the second horizontal portion of the first gate insulating layer, and   wherein a portion of the third conductorization region is self-aligned with the second slope portion of the first gate insulating layer.   
     
     
         35 . The display device of  claim 33 , wherein the second conductorization region does not overlap the first or second gate electrode. 
     
     
         36 . The display device of  claim 33 , wherein the first conductorization region overlaps the first slope of the buffer layer,
 wherein the third conductorization region overlaps the second slope of the buffer layer, and   wherein the second conductorization region does not overlap the first or second slope of the buffer layer.   
     
     
         37 . The display device of  claim 33 , wherein the first conductorization region, the second conductorization region, and the third conductorization region are spaced apart from each other in a direction parallel to the top surface of the substrate. 
     
     
         38 . The display device of  claim 33 , further comprising a third thin-film transistor disposed over the buffer layer,
 wherein the third thin-film transistor comprises:
 a second active pattern disposed over the buffer layer; 
 a second gate insulating layer disposed over the second active pattern; and 
 a second gate electrode disposed over a portion of the second gate insulating layer.